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brw: don't generate invalid instructions

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0e3e5146cf ("intel/brw: Use correct instruction for value change check
when coalescing") enabled some new cases that exposed a pre-existing
bug that would turn something like this :

      mul.sat(16) %789:F, %787:F, %788:F
      mov.g.f0.0(16) %790:F, %789:F
      (+f0.0) sel(16) %800:UD, %790:UD, 0u

into this :

      mul.sat(16) %790:F, %787:F, %788:F
      mov.g.f0.0(16) null:F, null<8,8,1>:F
      (+f0.0) sel(16) %800:UD, %790:UD, 0u

The mov[] array can contain the same instruction because it's repeated
for each REG_SIZE writes and a SIMD16 instruction will write 2
REG_SIZE.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0e3e5146cf ("intel/brw: Use correct instruction for value change check when coalescing")
Cc: mesa-stable
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35276>
This commit is contained in:
Lionel Landwerlin 2025-06-02 10:13:29 +03:00 • committed by Marge Bot
parent 2bb9b94c4c
commit a51d061c00
2 changed files with 51 additions and 1 deletions
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2
src/intel/compiler/brw_opt_register_coalesce.cpp
View file

@ -332,7 +332,7 @@ brw_opt_register_coalesce(brw_shader &s)
progress = true;
for (int i = 0; i < src_size; i++) {
for (int i = 0; i < src_size; i += regs_written(mov[i])) {
if (!mov[i])
continue;

50
src/intel/compiler/test_opt_register_coalesce.cpp
View file

@ -109,3 +109,53 @@ TEST_F(RegisterCoalesceTest, ChangingTemporaryCompoundRegisterNotChangesOriginal
EXPECT_NO_PROGRESS(brw_opt_register_coalesce, bld);
}
TEST_F(RegisterCoalesceTest, MovWithFlagRegisterWrite)
{
brw_builder bld = make_shader(MESA_SHADER_COMPUTE, 16);
brw_builder exp = make_shader(MESA_SHADER_COMPUTE, 16);
/**
* mul.sat(16) %789:F, %787:F, %788:F
* mov.g.f0.0(16) %790:F, %789:F
* (+f0.0) sel(16) %800:UD, %790:UD, 0u
*/
brw_reg src0 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg src1 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg vgrf0 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg vgrf1 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg vgrf2 = vgrf(bld, exp, BRW_TYPE_F);
{
brw_inst *mul = bld.MUL(vgrf0, src0, src1);
mul->saturate = true;
brw_inst *mov = bld.MOV(vgrf1, vgrf0);
mov->conditional_mod = BRW_CONDITIONAL_G;
brw_inst *sel = bld.SEL(vgrf2, vgrf1, brw_imm_f(0.0));
sel->predicate = BRW_PREDICATE_NORMAL;
}
EXPECT_PROGRESS(brw_opt_register_coalesce, bld);
/**
* mul.sat(16) %789:F, %787:F, %788:F
* mov.g.f0.0(16) null:F, %789:F
* (+f0.0) sel(16) %800:UD, %789:UD, 0u
*/
{
brw_inst *mul = exp.MUL(vgrf0, src0, src1);
mul->saturate = true;
brw_inst *mov = exp.MOV(brw_null_reg(), vgrf0);
mov->conditional_mod = BRW_CONDITIONAL_G;
brw_inst *sel = exp.SEL(vgrf2, vgrf0, brw_imm_f(0.0));
sel->predicate = BRW_PREDICATE_NORMAL;
}
EXPECT_SHADERS_MATCH(bld, exp);
}