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brw: Fix MAD instruction usage in spilling logic
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The intention here is to build a SIMD8 value, that will be expanded
as needed -- just like the SHL/ADD case, but with a single instruction.

Found when the was triggering invalid MAD with SIMD32 (that gets compressed)
*and* with overlapping destination and source *and* which would cause
conflict when divided into two SIMD16.

Fixes: 338273dedd ("brw/reg_allocate: Optimize spill offset calculation using integer MAD")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35302>
This commit is contained in:
Caio Oliveira 2025-06-02 15:59:34 -07:00 • committed by Marge Bot
parent 9c0ff88e8d
commit 80fb555718
1 changed files with 4 additions and 4 deletions
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8
src/intel/compiler/brw_reg_allocate.cpp
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@ -738,10 +738,10 @@ brw_reg_alloc::build_lane_offsets(const brw_builder &bld, uint32_t spill_offset,
_mesa_set_add(spill_insts, inst);
if (spill_offset > 0 && spill_offset <= 0xffffu) {
inst = ubld.MAD(offset,
brw_imm_uw(spill_offset),
retype(offset, BRW_TYPE_UW),
brw_imm_uw(4));
inst = ubld.group(8, 0).MAD(offset,
brw_imm_uw(spill_offset),
retype(offset, BRW_TYPE_UW),
brw_imm_uw(4));
_mesa_set_add(spill_insts, inst);
} else {
/* Make the offset a dword */