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intel/brw: Rename brw_inst_* helpers to brw_eu_inst_*

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Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32643>
This commit is contained in:
Caio Oliveira 2024-12-06 12:50:23 -08:00 • committed by Marge Bot
parent 3031b22a8a
commit 228aba779f
13 changed files with 1391 additions and 1388 deletions
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12
src/intel/compiler/brw_asm.c
View file

@ -35,7 +35,7 @@ i965_postprocess_labels()
int relative_offset = (tlabel->offset - ilabel->offset) / sizeof(brw_eu_inst);
relative_offset *= to_bytes_scale;
unsigned opcode = brw_inst_opcode(p->isa, inst);
unsigned opcode = brw_eu_inst_opcode(p->isa, inst);
if (ilabel->type == INSTR_LABEL_JIP) {
switch (opcode) {
@ -43,12 +43,12 @@ i965_postprocess_labels()
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
brw_inst_set_jip(p->devinfo, inst, relative_offset);
brw_eu_inst_set_jip(p->devinfo, inst, relative_offset);
break;
case BRW_OPCODE_BREAK:
case BRW_OPCODE_HALT:
case BRW_OPCODE_CONTINUE:
brw_inst_set_jip(p->devinfo, inst, relative_offset);
brw_eu_inst_set_jip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with JIP label\n", opcode);
@ -58,7 +58,7 @@ i965_postprocess_labels()
switch (opcode) {
case BRW_OPCODE_IF:
case BRW_OPCODE_ELSE:
brw_inst_set_uip(p->devinfo, inst, relative_offset);
brw_eu_inst_set_uip(p->devinfo, inst, relative_offset);
break;
case BRW_OPCODE_WHILE:
case BRW_OPCODE_ENDIF:
@ -67,7 +67,7 @@ i965_postprocess_labels()
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
brw_inst_set_uip(p->devinfo, inst, relative_offset);
brw_eu_inst_set_uip(p->devinfo, inst, relative_offset);
break;
default:
fprintf(stderr, "Unknown opcode %d with UIP label\n", opcode);
@ -144,7 +144,7 @@ brw_assemble(void *mem_ctx, const struct intel_device_info *devinfo,
int compacted = 0;
for (int i = 0; i < result.inst_count; i++) {
const brw_eu_inst *inst = result.bin + i;
if (brw_inst_cmpt_control(devinfo, inst))
if (brw_eu_inst_cmpt_control(devinfo, inst))
compacted++;
}
result.bin_size -= compacted * 8;

2
src/intel/compiler/brw_asm_tool.c
View file

@ -241,7 +241,7 @@ int main(int argc, char **argv)
const brw_eu_inst *insn = r.bin + offset;
bool compacted = false;
if (compact && brw_inst_cmpt_control(devinfo, insn)) {
if (compact && brw_eu_inst_cmpt_control(devinfo, insn)) {
offset += 8;
compacted = true;
} else {

560
src/intel/compiler/brw_disasm.c
View file

File diff suppressed because it is too large Load diff

28
src/intel/compiler/brw_eu.c
View file

@ -187,17 +187,17 @@ void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
* [group, group + exec_size) to the instruction passed as argument.
*/
void
brw_inst_set_group(const struct intel_device_info *devinfo,
brw_eu_inst_set_group(const struct intel_device_info *devinfo,
brw_eu_inst *inst, unsigned group)
{
if (devinfo->ver >= 20) {
assert(group % 8 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
brw_eu_inst_set_qtr_control(devinfo, inst, group / 8);
} else {
assert(group % 4 == 0 && group < 32);
brw_inst_set_qtr_control(devinfo, inst, group / 8);
brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
brw_eu_inst_set_qtr_control(devinfo, inst, group / 8);
brw_eu_inst_set_nib_control(devinfo, inst, (group / 4) % 2);
}
}
@ -448,7 +448,7 @@ brw_label_assembly(const struct brw_isa_info *isa,
const brw_eu_inst *inst = (const brw_eu_inst *) ((const char *) assembly + offset);
brw_eu_inst uncompacted;
bool is_compact = brw_inst_cmpt_control(devinfo, inst);
bool is_compact = brw_eu_inst_cmpt_control(devinfo, inst);
if (is_compact) {
brw_eu_compact_inst *compacted = (brw_eu_compact_inst *)inst;
@ -456,14 +456,14 @@ brw_label_assembly(const struct brw_isa_info *isa,
inst = &uncompacted;
}
if (brw_has_uip(devinfo, brw_inst_opcode(isa, inst))) {
if (brw_has_uip(devinfo, brw_eu_inst_opcode(isa, inst))) {
/* Instructions that have UIP also have JIP. */
brw_create_label(&root_label,
offset + brw_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
offset + brw_eu_inst_uip(devinfo, inst) * to_bytes_scale, mem_ctx);
brw_create_label(&root_label,
offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
} else if (brw_has_jip(devinfo, brw_inst_opcode(isa, inst))) {
int jip = brw_inst_jip(devinfo, inst);
offset + brw_eu_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx);
} else if (brw_has_jip(devinfo, brw_eu_inst_opcode(isa, inst))) {
int jip = brw_eu_inst_jip(devinfo, inst);
brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx);
}
@ -511,7 +511,7 @@ brw_disassemble(const struct brw_isa_info *isa,
}
}
bool compacted = brw_inst_cmpt_control(devinfo, insn);
bool compacted = brw_eu_inst_cmpt_control(devinfo, insn);
if (0)
fprintf(out, "0x%08x: ", offset);
@ -708,11 +708,11 @@ brw_num_sources_from_inst(const struct brw_isa_info *isa,
{
const struct intel_device_info *devinfo = isa->devinfo;
const struct opcode_desc *desc =
brw_opcode_desc(isa, brw_inst_opcode(isa, inst));
brw_opcode_desc(isa, brw_eu_inst_opcode(isa, inst));
unsigned math_function;
if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
math_function = brw_inst_math_function(devinfo, inst);
if (brw_eu_inst_opcode(isa, inst) == BRW_OPCODE_MATH) {
math_function = brw_eu_inst_math_function(devinfo, inst);
} else {
assert(desc->nsrc < 4);
return desc->nsrc;

4
src/intel/compiler/brw_eu.h
View file

@ -142,7 +142,7 @@ void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
void brw_set_default_saturate( struct brw_codegen *p, bool enable );
void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
void brw_inst_set_group(const struct intel_device_info *devinfo,
void brw_eu_inst_set_group(const struct intel_device_info *devinfo,
brw_eu_inst *inst, unsigned group);
void brw_set_default_group(struct brw_codegen *p, unsigned group);
void brw_set_default_predicate_control(struct brw_codegen *p, enum brw_predicate pc);
@ -1593,7 +1593,7 @@ next_offset(const struct intel_device_info *devinfo, void *store, int offset)
{
brw_eu_inst *insn = (brw_eu_inst *)((char *)store + offset);
if (brw_inst_cmpt_control(devinfo, insn))
if (brw_eu_inst_cmpt_control(devinfo, insn))
return offset + 8;
else
return offset + 16;

142
src/intel/compiler/brw_eu_compact.c
View file

@ -1339,9 +1339,9 @@ has_unmapped_bits(const struct brw_isa_info *isa, const brw_eu_inst *src)
const struct intel_device_info *devinfo = isa->devinfo;
/* EOT can only be mapped on a send if the src1 is an immediate */
if ((brw_inst_opcode(isa, src) == BRW_OPCODE_SENDC ||
brw_inst_opcode(isa, src) == BRW_OPCODE_SEND) &&
brw_inst_eot(devinfo, src))
if ((brw_eu_inst_opcode(isa, src) == BRW_OPCODE_SENDC ||
brw_eu_inst_opcode(isa, src) == BRW_OPCODE_SEND) &&
brw_eu_inst_eot(devinfo, src))
return true;
/* Check for instruction bits that don't map to any of the fields of the
@ -1393,14 +1393,14 @@ brw_try_compact_3src_instruction(const struct brw_isa_info *isa,
{
const struct intel_device_info *devinfo = isa->devinfo;
bool is_dpas = brw_inst_opcode(isa, src) == BRW_OPCODE_DPAS;
bool is_dpas = brw_eu_inst_opcode(isa, src) == BRW_OPCODE_DPAS;
if (has_3src_unmapped_bits(devinfo, src, is_dpas))
return false;
#define compact(field) \
brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_##field(devinfo, src))
brw_compact_inst_set_3src_##field(devinfo, dst, brw_eu_inst_3src_##field(devinfo, src))
#define compact_a16(field) \
brw_compact_inst_set_3src_##field(devinfo, dst, brw_inst_3src_a16_##field(devinfo, src))
brw_compact_inst_set_3src_##field(devinfo, dst, brw_eu_inst_3src_a16_##field(devinfo, src))
compact(hw_opcode);
@ -1571,11 +1571,11 @@ static bool
has_immediate(const struct intel_device_info *devinfo, const brw_eu_inst *inst,
enum brw_reg_type *type)
{
if (brw_inst_src0_reg_file(devinfo, inst) == IMM) {
*type = brw_inst_src0_type(devinfo, inst);
if (brw_eu_inst_src0_reg_file(devinfo, inst) == IMM) {
*type = brw_eu_inst_src0_type(devinfo, inst);
return *type != BRW_TYPE_INVALID;
} else if (brw_inst_src1_reg_file(devinfo, inst) == IMM) {
*type = brw_inst_src1_type(devinfo, inst);
} else if (brw_eu_inst_src1_reg_file(devinfo, inst) == IMM) {
*type = brw_eu_inst_src1_type(devinfo, inst);
return *type != BRW_TYPE_INVALID;
}
@ -1596,26 +1596,26 @@ precompact(const struct brw_isa_info *isa, brw_eu_inst inst)
* sequential elements, so convert to those before compacting.
*/
if (devinfo->verx10 >= 125) {
if (brw_inst_src0_reg_file(devinfo, &inst) == FIXED_GRF &&
brw_inst_src0_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
brw_inst_src0_vstride(devinfo, &inst) == (brw_inst_src0_width(devinfo, &inst) + 1) &&
brw_inst_src0_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
brw_inst_set_src0_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
brw_inst_set_src0_width(devinfo, &inst, BRW_WIDTH_1);
brw_inst_set_src0_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
if (brw_eu_inst_src0_reg_file(devinfo, &inst) == FIXED_GRF &&
brw_eu_inst_src0_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
brw_eu_inst_src0_vstride(devinfo, &inst) == (brw_eu_inst_src0_width(devinfo, &inst) + 1) &&
brw_eu_inst_src0_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
brw_eu_inst_set_src0_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
brw_eu_inst_set_src0_width(devinfo, &inst, BRW_WIDTH_1);
brw_eu_inst_set_src0_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
}
if (brw_inst_src1_reg_file(devinfo, &inst) == FIXED_GRF &&
brw_inst_src1_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
brw_inst_src1_vstride(devinfo, &inst) == (brw_inst_src1_width(devinfo, &inst) + 1) &&
brw_inst_src1_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
brw_inst_set_src1_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
brw_inst_set_src1_width(devinfo, &inst, BRW_WIDTH_1);
brw_inst_set_src1_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
if (brw_eu_inst_src1_reg_file(devinfo, &inst) == FIXED_GRF &&
brw_eu_inst_src1_vstride(devinfo, &inst) > BRW_VERTICAL_STRIDE_1 &&
brw_eu_inst_src1_vstride(devinfo, &inst) == (brw_eu_inst_src1_width(devinfo, &inst) + 1) &&
brw_eu_inst_src1_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
brw_eu_inst_set_src1_vstride(devinfo, &inst, BRW_VERTICAL_STRIDE_1);
brw_eu_inst_set_src1_width(devinfo, &inst, BRW_WIDTH_1);
brw_eu_inst_set_src1_hstride(devinfo, &inst, BRW_HORIZONTAL_STRIDE_0);
}
}
if (brw_inst_src0_reg_file(devinfo, &inst) != IMM)
if (brw_eu_inst_src0_reg_file(devinfo, &inst) != IMM)
return inst;
/* The Bspec's section titled "Non-present Operands" claims that if src0
@ -1640,10 +1640,10 @@ precompact(const struct brw_isa_info *isa, brw_eu_inst inst)
* overlap with the immediate and setting them would overwrite the
* immediate we set.
*/
if (!(brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_DF ||
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_UQ ||
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_Q)) {
brw_inst_set_src1_reg_hw_type(devinfo, &inst, 0);
if (!(brw_eu_inst_src0_type(devinfo, &inst) == BRW_TYPE_DF ||
brw_eu_inst_src0_type(devinfo, &inst) == BRW_TYPE_UQ ||
brw_eu_inst_src0_type(devinfo, &inst) == BRW_TYPE_Q)) {
brw_eu_inst_set_src1_reg_hw_type(devinfo, &inst, 0);
}
/* Compacted instructions only have 12-bits (plus 1 for the other 20)
@ -1661,12 +1661,12 @@ precompact(const struct brw_isa_info *isa, brw_eu_inst inst)
* removing the need for this.
*/
if (devinfo->ver < 12 &&
brw_inst_imm_ud(devinfo, &inst) == 0x0 &&
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_F &&
brw_inst_dst_type(devinfo, &inst) == BRW_TYPE_F &&
brw_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
enum brw_reg_file file = brw_inst_src0_reg_file(devinfo, &inst);
brw_inst_set_src0_file_type(devinfo, &inst, file, BRW_TYPE_VF);
brw_eu_inst_imm_ud(devinfo, &inst) == 0x0 &&
brw_eu_inst_src0_type(devinfo, &inst) == BRW_TYPE_F &&
brw_eu_inst_dst_type(devinfo, &inst) == BRW_TYPE_F &&
brw_eu_inst_dst_hstride(devinfo, &inst) == BRW_HORIZONTAL_STRIDE_1) {
enum brw_reg_file file = brw_eu_inst_src0_reg_file(devinfo, &inst);
brw_eu_inst_set_src0_file_type(devinfo, &inst, file, BRW_TYPE_VF);
}
/* There are no mappings for dst:d | i:d, so if the immediate is suitable
@ -1676,15 +1676,15 @@ precompact(const struct brw_isa_info *isa, brw_eu_inst inst)
*/
if (devinfo->ver < 12 &&
compact_immediate(devinfo, BRW_TYPE_D,
brw_inst_imm_ud(devinfo, &inst)) != -1 &&
brw_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
brw_inst_src0_type(devinfo, &inst) == BRW_TYPE_D &&
brw_inst_dst_type(devinfo, &inst) == BRW_TYPE_D) {
enum brw_reg_file src_file = brw_inst_src0_reg_file(devinfo, &inst);
enum brw_reg_file dst_file = brw_inst_dst_reg_file(devinfo, &inst);
brw_eu_inst_imm_ud(devinfo, &inst)) != -1 &&
brw_eu_inst_cond_modifier(devinfo, &inst) == BRW_CONDITIONAL_NONE &&
brw_eu_inst_src0_type(devinfo, &inst) == BRW_TYPE_D &&
brw_eu_inst_dst_type(devinfo, &inst) == BRW_TYPE_D) {
enum brw_reg_file src_file = brw_eu_inst_src0_reg_file(devinfo, &inst);
enum brw_reg_file dst_file = brw_eu_inst_dst_reg_file(devinfo, &inst);
brw_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_TYPE_UD);
brw_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_TYPE_UD);
brw_eu_inst_set_src0_file_type(devinfo, &inst, src_file, BRW_TYPE_UD);
brw_eu_inst_set_dst_file_type(devinfo, &inst, dst_file, BRW_TYPE_UD);
}
return inst;
@ -1703,9 +1703,9 @@ try_compact_instruction(const struct compaction_state *c,
const struct intel_device_info *devinfo = c->isa->devinfo;
brw_eu_compact_inst temp;
assert(brw_inst_cmpt_control(devinfo, src) == 0);
assert(brw_eu_inst_cmpt_control(devinfo, src) == 0);
if (is_3src(c->isa, brw_inst_opcode(c->isa, src))) {
if (is_3src(c->isa, brw_eu_inst_opcode(c->isa, src))) {
memset(&temp, 0, sizeof(temp));
if (brw_try_compact_3src_instruction(c->isa, &temp, src)) {
*dst = temp;
@ -1722,7 +1722,7 @@ try_compact_instruction(const struct compaction_state *c,
if (is_immediate) {
compacted_imm = compact_immediate(devinfo, type,
brw_inst_imm_ud(devinfo, src));
brw_eu_inst_imm_ud(devinfo, src));
if (compacted_imm == -1)
return false;
}
@ -1733,10 +1733,10 @@ try_compact_instruction(const struct compaction_state *c,
memset(&temp, 0, sizeof(temp));
#define compact(field) \
brw_compact_inst_set_##field(devinfo, &temp, brw_inst_##field(devinfo, src))
brw_compact_inst_set_##field(devinfo, &temp, brw_eu_inst_##field(devinfo, src))
#define compact_reg(field) \
brw_compact_inst_set_##field##_reg_nr(devinfo, &temp, \
brw_inst_##field##_da_reg_nr(devinfo, src))
brw_eu_inst_##field##_da_reg_nr(devinfo, src))
compact(hw_opcode);
compact(debug_control);
@ -2085,9 +2085,9 @@ brw_uncompact_3src_instruction(const struct compaction_state *c,
const struct intel_device_info *devinfo = c->isa->devinfo;
#define uncompact(field) \
brw_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
brw_eu_inst_set_3src_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
#define uncompact_a16(field) \
brw_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
brw_eu_inst_set_3src_a16_##field(devinfo, dst, brw_compact_inst_3src_##field(devinfo, src))
uncompact(hw_opcode);
@ -2119,7 +2119,7 @@ brw_uncompact_3src_instruction(const struct compaction_state *c,
uncompact_a16(src1_subreg_nr);
uncompact_a16(src2_subreg_nr);
}
brw_inst_set_3src_cmpt_control(devinfo, dst, false);
brw_eu_inst_set_3src_cmpt_control(devinfo, dst, false);
#undef uncompact
#undef uncompact_a16
@ -2141,9 +2141,9 @@ uncompact_instruction(const struct compaction_state *c, brw_eu_inst *dst,
}
#define uncompact(field) \
brw_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
brw_eu_inst_set_##field(devinfo, dst, brw_compact_inst_##field(devinfo, src))
#define uncompact_reg(field) \
brw_inst_set_##field##_da_reg_nr(devinfo, dst, \
brw_eu_inst_set_##field##_da_reg_nr(devinfo, dst, \
brw_compact_inst_##field##_reg_nr(devinfo, src))
uncompact(hw_opcode);
@ -2158,7 +2158,7 @@ uncompact_instruction(const struct compaction_state *c, brw_eu_inst *dst,
if (has_immediate(devinfo, dst, &type)) {
unsigned imm = uncompact_immediate(devinfo, type,
brw_compact_inst_imm(devinfo, src));
brw_inst_set_imm_ud(devinfo, dst, imm);
brw_eu_inst_set_imm_ud(devinfo, dst, imm);
} else {
set_uncompacted_src1(c, dst, src);
uncompact_reg(src1);
@ -2176,7 +2176,7 @@ uncompact_instruction(const struct compaction_state *c, brw_eu_inst *dst,
uncompact_reg(dst);
uncompact_reg(src0);
}
brw_inst_set_cmpt_control(devinfo, dst, false);
brw_eu_inst_set_cmpt_control(devinfo, dst, false);
#undef uncompact
#undef uncompact_reg
@ -2240,24 +2240,24 @@ update_uip_jip(const struct brw_isa_info *isa, brw_eu_inst *insn,
/* Even though the values are signed, we don't need the rounding behavior
* of integer division. The shifts are safe.
*/
assert(brw_inst_jip(devinfo, insn) % 8 == 0 &&
brw_inst_uip(devinfo, insn) % 8 == 0);
assert(brw_eu_inst_jip(devinfo, insn) % 8 == 0 &&
brw_eu_inst_uip(devinfo, insn) % 8 == 0);
int32_t jip_compacted = brw_inst_jip(devinfo, insn) >> shift;
int32_t jip_compacted = brw_eu_inst_jip(devinfo, insn) >> shift;
jip_compacted -= compacted_between(this_old_ip,
this_old_ip + (jip_compacted / 2),
compacted_counts);
brw_inst_set_jip(devinfo, insn, (uint32_t)jip_compacted << shift);
brw_eu_inst_set_jip(devinfo, insn, (uint32_t)jip_compacted << shift);
if (brw_inst_opcode(isa, insn) == BRW_OPCODE_ENDIF ||
brw_inst_opcode(isa, insn) == BRW_OPCODE_WHILE)
if (brw_eu_inst_opcode(isa, insn) == BRW_OPCODE_ENDIF ||
brw_eu_inst_opcode(isa, insn) == BRW_OPCODE_WHILE)
return;
int32_t uip_compacted = brw_inst_uip(devinfo, insn) >> shift;
int32_t uip_compacted = brw_eu_inst_uip(devinfo, insn) >> shift;
uip_compacted -= compacted_between(this_old_ip,
this_old_ip + (uip_compacted / 2),
compacted_counts);
brw_inst_set_uip(devinfo, insn, (uint32_t)uip_compacted << shift);
brw_eu_inst_set_uip(devinfo, insn, (uint32_t)uip_compacted << shift);
}
static void
@ -2407,7 +2407,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
int this_old_ip = old_ip[offset / sizeof(brw_eu_compact_inst)];
int this_compacted_count = compacted_counts[this_old_ip];
switch (brw_inst_opcode(p->isa, insn)) {
switch (brw_eu_inst_opcode(p->isa, insn)) {
case BRW_OPCODE_BREAK:
case BRW_OPCODE_CONTINUE:
case BRW_OPCODE_HALT:
@ -2418,7 +2418,7 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
case BRW_OPCODE_ELSE:
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_WHILE:
if (brw_inst_cmpt_control(devinfo, insn)) {
if (brw_eu_inst_cmpt_control(devinfo, insn)) {
brw_eu_inst uncompacted;
uncompact_instruction(&c, &uncompacted,
(brw_eu_compact_inst *)insn);
@ -2439,20 +2439,20 @@ brw_compact_instructions(struct brw_codegen *p, int start_offset,
* and Gens that use this cannot compact instructions with immediate
* operands.
*/
if (brw_inst_cmpt_control(devinfo, insn))
if (brw_eu_inst_cmpt_control(devinfo, insn))
break;
if (brw_inst_dst_reg_file(devinfo, insn) == ARF &&
brw_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) {
assert(brw_inst_src1_reg_file(devinfo, insn) == IMM);
if (brw_eu_inst_dst_reg_file(devinfo, insn) == ARF &&
brw_eu_inst_dst_da_reg_nr(devinfo, insn) == BRW_ARF_IP) {
assert(brw_eu_inst_src1_reg_file(devinfo, insn) == IMM);
int shift = 3;
int jump_compacted = brw_inst_imm_d(devinfo, insn) >> shift;
int jump_compacted = brw_eu_inst_imm_d(devinfo, insn) >> shift;
int target_old_ip = this_old_ip + (jump_compacted / 2);
int target_compacted_count = compacted_counts[target_old_ip];
jump_compacted -= (target_compacted_count - this_compacted_count);
brw_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
brw_eu_inst_set_imm_ud(devinfo, insn, jump_compacted << shift);
}
break;

608
src/intel/compiler/brw_eu_emit.c
View file

File diff suppressed because it is too large Load diff

249
src/intel/compiler/brw_eu_inst.h
View file

@ -55,8 +55,8 @@ static inline void brw_eu_inst_set_bits(brw_eu_inst *inst,
#define FC(name, hi9, lo9, hi12, lo12, assertions) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
{ \
assert(assertions); \
if (devinfo->ver >= 12) \
@ -65,8 +65,8 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst_set_bits(inst, hi9, lo9, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
assert(assertions); \
if (devinfo->ver >= 12) \
@ -85,8 +85,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
*/
#define F20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
{ \
if (devinfo->ver >= 20) \
brw_eu_inst_set_bits(inst, hi20, lo20, v); \
@ -96,8 +96,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
brw_eu_inst_set_bits(inst, hi9, lo9, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
if (devinfo->ver >= 20) \
return brw_eu_inst_bits(inst, hi20, lo20); \
@ -109,8 +109,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
#define FV20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
{ \
if (devinfo->ver >= 20) \
brw_eu_inst_set_bits(inst, hi20, lo20, v & 0x7); \
@ -120,8 +120,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
brw_eu_inst_set_bits(inst, hi9, lo9, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
if (devinfo->ver >= 20) \
return brw_eu_inst_bits(inst, hi20, lo20) == 0x7 ? 0xF : \
@ -134,8 +134,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
#define FD20(name, hi9, lo9, hi12, lo12, hi20, lo20, zero20) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
{ \
if (devinfo->ver >= 20) { \
brw_eu_inst_set_bits(inst, hi20, lo20, v >> 1); \
@ -149,8 +149,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
brw_eu_inst_set_bits(inst, hi9, lo9, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
if (devinfo->ver >= 20) \
return (brw_eu_inst_bits(inst, hi20, lo20) << 1) | \
@ -167,8 +167,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
*/
#define FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t value) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t value) \
{ \
assert(assertions); \
if (devinfo->ver >= 12) { \
@ -181,8 +181,8 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \
} \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
assert(assertions); \
if (devinfo->ver >= 12) { \
@ -237,8 +237,8 @@ hw_reg_file_to_brw_reg_file(uint64_t v)
*/
#define FFC(name, hi9, lo9, hi12, lo12, assertions, ...) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_file file) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_file file) \
{ \
assert(assertions); \
const struct { \
@ -265,8 +265,8 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \
} \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
assert(assertions); \
const struct { \
@ -298,8 +298,8 @@ brw_inst_##name(const struct intel_device_info *devinfo, \
*/
#define FK(name, hi9, lo9, const12) \
static inline void \
brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
brw_eu_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, uint64_t v) \
{ \
if (devinfo->ver >= 12) \
assert(v == (const12)); \
@ -307,8 +307,8 @@ brw_inst_set_##name(const struct intel_device_info *devinfo, \
brw_eu_inst_set_bits(inst, hi9, lo9, v); \
} \
static inline uint64_t \
brw_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##name(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
if (devinfo->ver >= 12) \
return (const12); \
@ -438,10 +438,10 @@ F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
#define F_3SRC_A16_SUBREG_NR(srcN, src_base) \
static inline void \
brw_inst_set_3src_a16_##srcN##_subreg_nr(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, \
unsigned value) \
brw_eu_inst_set_3src_a16_##srcN##_subreg_nr(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, \
unsigned value) \
{ \
assert(devinfo->ver == 9); \
assert((value & ~0b11110) == 0); \
@ -449,7 +449,7 @@ brw_inst_set_3src_a16_##srcN##_subreg_nr(const struct \
brw_eu_inst_set_bits(inst, src_base + 20, src_base + 20, (value >> 1) & 1); \
} \
static inline unsigned \
brw_inst_3src_a16_##srcN##_subreg_nr(const struct \
brw_eu_inst_3src_a16_##srcN##_subreg_nr(const struct \
intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
@ -465,18 +465,19 @@ F_3SRC_A16_SUBREG_NR(src2, 106)
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_type type) \
brw_eu_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, \
enum brw_reg_type type) \
{ \
unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
brw_eu_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
} \
\
static inline enum brw_reg_type \
brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
unsigned hw_type = brw_eu_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
return brw_type_decode_for_3src(devinfo, hw_type, 0); \
}
@ -527,29 +528,30 @@ FC(3src_a1_exec_type, /* 9+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_type type) \
brw_eu_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, \
enum brw_reg_type type) \
{ \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
inst); \
if (brw_type_is_float(type)) { \
(enum gfx10_align1_3src_exec_type) \
brw_eu_inst_3src_a1_exec_type(devinfo, inst); \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
} else { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
} \
unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
brw_eu_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
} \
\
static inline enum brw_reg_type \
brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
inst); \
unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
(enum gfx10_align1_3src_exec_type) \
brw_eu_inst_3src_a1_exec_type(devinfo, inst); \
unsigned hw_type = brw_eu_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
}
@ -564,7 +566,7 @@ REG_TYPE(src2)
* @{
*/
static inline uint16_t
brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
const brw_eu_inst *insn)
{
assert(devinfo->ver >= 10);
@ -575,7 +577,7 @@ brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
}
static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
const brw_eu_inst *insn)
{
assert(devinfo->ver >= 10);
@ -586,7 +588,7 @@ brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst *insn, uint16_t value)
{
assert(devinfo->ver >= 10);
@ -597,7 +599,7 @@ brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
brw_eu_inst *insn, uint16_t value)
{
assert(devinfo->ver >= 10);
@ -637,29 +639,30 @@ F(dpas_3src_dst_hw_type, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_type type)\
brw_eu_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, \
enum brw_reg_type type) \
{ \
UNUSED enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
inst); \
if (brw_type_is_float(type)) { \
(enum gfx10_align1_3src_exec_type) \
brw_eu_inst_dpas_3src_exec_type(devinfo, inst); \
if (brw_type_is_float(type)) { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
} else { \
assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
} \
unsigned hw_type = brw_type_encode_for_3src(devinfo, type); \
brw_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \
brw_eu_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \
} \
\
static inline enum brw_reg_type \
brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
enum gfx10_align1_3src_exec_type exec_type = \
(enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
inst); \
unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
(enum gfx10_align1_3src_exec_type) \
brw_eu_inst_dpas_3src_exec_type(devinfo, inst); \
unsigned hw_type = brw_eu_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
return brw_type_decode_for_3src(devinfo, hw_type, exec_type); \
}
@ -674,33 +677,33 @@ REG_TYPE(src2)
* @{
*/
static inline void
brw_inst_set_uip(const struct intel_device_info *devinfo,
brw_eu_inst_set_uip(const struct intel_device_info *devinfo,
brw_eu_inst *inst, int32_t value)
{
if (devinfo->ver >= 12)
brw_inst_set_src1_is_imm(devinfo, inst, 1);
brw_eu_inst_set_src1_is_imm(devinfo, inst, 1);
brw_eu_inst_set_bits(inst, 95, 64, (uint32_t)value);
}
static inline int32_t
brw_inst_uip(const struct intel_device_info *devinfo, const brw_eu_inst *inst)
brw_eu_inst_uip(const struct intel_device_info *devinfo, const brw_eu_inst *inst)
{
return brw_eu_inst_bits(inst, 95, 64);
}
static inline void
brw_inst_set_jip(const struct intel_device_info *devinfo,
brw_eu_inst_set_jip(const struct intel_device_info *devinfo,
brw_eu_inst *inst, int32_t value)
{
if (devinfo->ver >= 12)
brw_inst_set_src0_is_imm(devinfo, inst, 1);
brw_eu_inst_set_src0_is_imm(devinfo, inst, 1);
brw_eu_inst_set_bits(inst, 127, 96, (uint32_t)value);
}
static inline int32_t
brw_inst_jip(const struct intel_device_info *devinfo, const brw_eu_inst *inst)
brw_eu_inst_jip(const struct intel_device_info *devinfo, const brw_eu_inst *inst)
{
return brw_eu_inst_bits(inst, 127, 96);
}
@ -745,7 +748,7 @@ FC(send_src0_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx
* separately.
*/
static inline void
brw_inst_set_send_desc(const struct intel_device_info *devinfo,
brw_eu_inst_set_send_desc(const struct intel_device_info *devinfo,
brw_eu_inst *inst, uint32_t value)
{
if (devinfo->ver >= 12) {
@ -763,10 +766,10 @@ brw_inst_set_send_desc(const struct intel_device_info *devinfo,
/**
* Get the SEND(C) message descriptor immediate.
*
* \sa brw_inst_set_send_desc().
* \sa brw_eu_inst_set_send_desc().
*/
static inline uint32_t
brw_inst_send_desc(const struct intel_device_info *devinfo,
brw_eu_inst_send_desc(const struct intel_device_info *devinfo,
const brw_eu_inst *inst)
{
if (devinfo->ver >= 12) {
@ -790,8 +793,8 @@ brw_inst_send_desc(const struct intel_device_info *devinfo,
* separately.
*/
static inline void
brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
brw_eu_inst *inst, uint32_t value, bool gather)
brw_eu_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
brw_eu_inst *inst, uint32_t value, bool gather)
{
assert(!gather || devinfo->ver >= 30);
@ -832,11 +835,11 @@ brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
* separately.
*/
static inline void
brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
brw_eu_inst *inst, uint32_t value, bool gather)
brw_eu_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
brw_eu_inst *inst, uint32_t value, bool gather)
{
if (devinfo->ver >= 12) {
brw_inst_set_send_ex_desc(devinfo, inst, value, gather);
brw_eu_inst_set_send_ex_desc(devinfo, inst, value, gather);
} else {
brw_eu_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
assert(GET_BITS(value, 15, 10) == 0);
@ -848,11 +851,11 @@ brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
/**
* Get the SEND(C) message extended descriptor immediate.
*
* \sa brw_inst_set_send_ex_desc().
* \sa brw_eu_inst_set_send_ex_desc().
*/
static inline uint32_t
brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
const brw_eu_inst *inst, bool gather)
brw_eu_inst_send_ex_desc(const struct intel_device_info *devinfo,
const brw_eu_inst *inst, bool gather)
{
assert(!gather || devinfo->ver >= 30);
@ -874,14 +877,14 @@ brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
/**
* Get the SENDS(C) message extended descriptor immediate.
*
* \sa brw_inst_set_send_ex_desc().
* \sa brw_eu_inst_set_send_ex_desc().
*/
static inline uint32_t
brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
const brw_eu_inst *inst, bool gather)
brw_eu_inst_sends_ex_desc(const struct intel_device_info *devinfo,
const brw_eu_inst *inst, bool gather)
{
if (devinfo->ver >= 12) {
return brw_inst_send_ex_desc(devinfo, inst, gather);
return brw_eu_inst_send_ex_desc(devinfo, inst, gather);
} else {
assert(!gather);
return (brw_eu_inst_bits(inst, 95, 80) << 16 |
@ -979,21 +982,21 @@ F(pi_message_data, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
* @{
*/
static inline int
brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
brw_eu_inst_imm_d(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
{
(void) devinfo;
return brw_eu_inst_bits(insn, 127, 96);
}
static inline unsigned
brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
brw_eu_inst_imm_ud(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
{
(void) devinfo;
return brw_eu_inst_bits(insn, 127, 96);
}
static inline uint64_t
brw_inst_imm_uq(const struct intel_device_info *devinfo,
brw_eu_inst_imm_uq(const struct intel_device_info *devinfo,
const brw_eu_inst *insn)
{
if (devinfo->ver >= 12) {
@ -1005,7 +1008,7 @@ brw_inst_imm_uq(const struct intel_device_info *devinfo,
}
static inline float
brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
brw_eu_inst_imm_f(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
{
union {
float f;
@ -1017,18 +1020,18 @@ brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
}
static inline double
brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
brw_eu_inst_imm_df(const struct intel_device_info *devinfo, const brw_eu_inst *insn)
{
union {
double d;
uint64_t u;
} dt;
dt.u = brw_inst_imm_uq(devinfo, insn);
dt.u = brw_eu_inst_imm_uq(devinfo, insn);
return dt.d;
}
static inline void
brw_inst_set_imm_d(const struct intel_device_info *devinfo,
brw_eu_inst_set_imm_d(const struct intel_device_info *devinfo,
brw_eu_inst *insn, int value)
{
(void) devinfo;
@ -1036,7 +1039,7 @@ brw_inst_set_imm_d(const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
brw_eu_inst_set_imm_ud(const struct intel_device_info *devinfo,
brw_eu_inst *insn, unsigned value)
{
(void) devinfo;
@ -1044,7 +1047,7 @@ brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_imm_f(const struct intel_device_info *devinfo,
brw_eu_inst_set_imm_f(const struct intel_device_info *devinfo,
brw_eu_inst *insn, float value)
{
union {
@ -1057,7 +1060,7 @@ brw_inst_set_imm_f(const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_imm_df(const struct intel_device_info *devinfo,
brw_eu_inst_set_imm_df(const struct intel_device_info *devinfo,
brw_eu_inst *insn, double value)
{
union {
@ -1076,7 +1079,7 @@ brw_inst_set_imm_df(const struct intel_device_info *devinfo,
}
static inline void
brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
brw_eu_inst_set_imm_uq(const struct intel_device_info *devinfo,
brw_eu_inst *insn, uint64_t value)
{
(void) devinfo;
@ -1092,24 +1095,24 @@ brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
#define REG_TYPE(reg) \
static inline void \
brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_file file, \
enum brw_reg_type type) \
brw_eu_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
brw_eu_inst *inst, enum brw_reg_file file, \
enum brw_reg_type type) \
{ \
assert(file <= IMM); \
assert(file <= IMM); \
unsigned hw_type = brw_type_encode(devinfo, file, type); \
brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
brw_eu_inst_set_##reg##_reg_file(devinfo, inst, file); \
brw_eu_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
} \
\
static inline enum brw_reg_type \
brw_inst_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##reg##_type(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
{ \
unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
(unsigned) FIXED_GRF : \
brw_inst_##reg##_reg_file(devinfo, inst); \
unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
(unsigned) FIXED_GRF : \
brw_eu_inst_##reg##_reg_file(devinfo, inst); \
unsigned hw_type = brw_eu_inst_##reg##_reg_hw_type(devinfo, inst); \
return brw_type_decode(devinfo, (enum brw_reg_file)file, hw_type); \
}
@ -1123,10 +1126,10 @@ REG_TYPE(src1)
#define BRW_IA1_ADDR_IMM(reg, g9_nine, g9_high, g9_low, \
g12_high, g12_low, g20_high, g20_low, g20_zero) \
static inline void \
brw_inst_set_##reg##_ia1_addr_imm(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, \
unsigned value) \
brw_eu_inst_set_##reg##_ia1_addr_imm(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, \
unsigned value) \
{ \
if (devinfo->ver >= 20) { \
assert((value & ~0x7ff) == 0); \
@ -1145,8 +1148,8 @@ brw_inst_set_##reg##_ia1_addr_imm(const struct \
} \
} \
static inline unsigned \
brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo,\
const brw_eu_inst *inst) \
{ \
if (devinfo->ver >= 20) { \
return brw_eu_inst_bits(inst, g20_high, g20_low) << 1 | \
@ -1168,9 +1171,9 @@ BRW_IA1_ADDR_IMM(dst, 47, 56, 48, 59, 50, 59, 50, 33)
#define BRW_IA16_ADDR_IMM(reg, g9_nine, g9_high, g9_low) \
static inline void \
brw_inst_set_##reg##_ia16_addr_imm(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, unsigned value) \
brw_eu_inst_set_##reg##_ia16_addr_imm(const struct \
intel_device_info *devinfo, \
brw_eu_inst *inst, unsigned value) \
{ \
assert(devinfo->ver < 12); \
assert((value & ~0x3ff) == 0); \
@ -1179,8 +1182,8 @@ brw_inst_set_##reg##_ia16_addr_imm(const struct \
brw_eu_inst_set_bits(inst, g9_nine, g9_nine, GET_BITS(value, 9, 9)); \
} \
static inline unsigned \
brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
const brw_eu_inst *inst) \
brw_eu_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo,\
const brw_eu_inst *inst) \
{ \
assert(devinfo->ver < 12); \
return (brw_eu_inst_bits(inst, g9_high, g9_low) << 4) | \
@ -1436,17 +1439,17 @@ F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
#undef F
static inline void
brw_inst_set_opcode(const struct brw_isa_info *isa,
brw_eu_inst_set_opcode(const struct brw_isa_info *isa,
struct brw_eu_inst *inst, enum opcode opcode)
{
brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
brw_eu_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
}
static inline enum opcode
brw_inst_opcode(const struct brw_isa_info *isa,
brw_eu_inst_opcode(const struct brw_isa_info *isa,
const struct brw_eu_inst *inst)
{
return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst));
return brw_opcode_decode(isa, brw_eu_inst_hw_opcode(isa->devinfo, inst));
}
#ifdef __cplusplus

276
src/intel/compiler/brw_eu_validate.c
View file

@ -256,9 +256,9 @@ invalid_values(const struct brw_isa_info *isa, const brw_hw_decoded_inst *inst)
struct string error_msg = { .str = NULL, .len = 0 };
if (devinfo->ver >= 12) {
unsigned qtr_ctrl = brw_inst_qtr_control(devinfo, inst->raw);
unsigned qtr_ctrl = brw_eu_inst_qtr_control(devinfo, inst->raw);
unsigned nib_ctrl =
devinfo->ver == 12 ? brw_inst_nib_control(devinfo, inst->raw) : 0;
devinfo->ver == 12 ? brw_eu_inst_nib_control(devinfo, inst->raw) : 0;
unsigned chan_off = (qtr_ctrl * 2 + nib_ctrl) << 2;
ERROR_IF(chan_off % inst->exec_size != 0,
@ -328,10 +328,10 @@ send_restrictions(const struct brw_isa_info *isa,
"src1 of split send must be a GRF or NULL");
if (devinfo->ver < 30) {
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
ERROR_IF(brw_eu_inst_eot(devinfo, inst->raw) &&
inst->src[0].nr < 112,
"send with EOT must use g112-g127");
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
ERROR_IF(brw_eu_inst_eot(devinfo, inst->raw) &&
inst->src[1].file == FIXED_GRF &&
inst->src[1].nr < 112,
"send with EOT must use g112-g127");
@ -340,14 +340,14 @@ send_restrictions(const struct brw_isa_info *isa,
if (inst->src[0].file == FIXED_GRF && inst->src[1].file == FIXED_GRF) {
/* Assume minimums if we don't know */
unsigned mlen = 1;
if (!brw_inst_send_sel_reg32_desc(devinfo, inst->raw)) {
const uint32_t desc = brw_inst_send_desc(devinfo, inst->raw);
if (!brw_eu_inst_send_sel_reg32_desc(devinfo, inst->raw)) {
const uint32_t desc = brw_eu_inst_send_desc(devinfo, inst->raw);
mlen = brw_message_desc_mlen(devinfo, desc) / reg_unit(devinfo);
}
unsigned ex_mlen = 1;
if (!brw_inst_send_sel_reg32_ex_desc(devinfo, inst->raw)) {
const uint32_t ex_desc = brw_inst_sends_ex_desc(devinfo, inst->raw, false);
if (!brw_eu_inst_send_sel_reg32_ex_desc(devinfo, inst->raw)) {
const uint32_t ex_desc = brw_eu_inst_sends_ex_desc(devinfo, inst->raw, false);
ex_mlen = brw_message_ex_desc_ex_mlen(devinfo, ex_desc) /
reg_unit(devinfo);
}
@ -365,13 +365,13 @@ send_restrictions(const struct brw_isa_info *isa,
ERROR_IF(inst->src[0].file != FIXED_GRF,
"send from non-GRF");
ERROR_IF(brw_inst_eot(devinfo, inst->raw) &&
ERROR_IF(brw_eu_inst_eot(devinfo, inst->raw) &&
inst->src[0].nr < 112,
"send with EOT must use g112-g127");
ERROR_IF(!dst_is_null(inst) &&
(inst->dst.nr + brw_inst_rlen(devinfo, inst->raw) > 127) &&
(inst->src[0].nr + brw_inst_mlen(devinfo, inst->raw) > inst->dst.nr),
(inst->dst.nr + brw_eu_inst_rlen(devinfo, inst->raw) > 127) &&
(inst->src[0].nr + brw_eu_inst_mlen(devinfo, inst->raw) > inst->dst.nr),
"r127 must not be used for return address when there is "
"a src and dest overlap");
}
@ -383,7 +383,7 @@ static bool
is_unsupported_inst(const struct brw_isa_info *isa,
const brw_eu_inst *inst)
{
return brw_inst_opcode(isa, inst) == BRW_OPCODE_ILLEGAL;
return brw_eu_inst_opcode(isa, inst) == BRW_OPCODE_ILLEGAL;
}
/**
@ -652,15 +652,15 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
*/
switch (s) {
case 0:
ERROR_IF(brw_inst_3src_a16_src0_rep_ctrl(devinfo, inst->raw),
ERROR_IF(brw_eu_inst_3src_a16_src0_rep_ctrl(devinfo, inst->raw),
"RepCtrl must be zero for 64-bit source 0");
break;
case 1:
ERROR_IF(brw_inst_3src_a16_src1_rep_ctrl(devinfo, inst->raw),
ERROR_IF(brw_eu_inst_3src_a16_src1_rep_ctrl(devinfo, inst->raw),
"RepCtrl must be zero for 64-bit source 1");
break;
case 2:
ERROR_IF(brw_inst_3src_a16_src2_rep_ctrl(devinfo, inst->raw),
ERROR_IF(brw_eu_inst_3src_a16_src2_rep_ctrl(devinfo, inst->raw),
"RepCtrl must be zero for 64-bit source 2");
break;
default: unreachable("invalid src");
@ -1581,7 +1581,7 @@ special_requirements_for_handling_double_precision_data_types(
if (is_double_precision &&
intel_device_info_is_9lp(devinfo)) {
ERROR_IF(inst->opcode == BRW_OPCODE_MAC ||
brw_inst_acc_wr_control(devinfo, inst->raw) ||
brw_eu_inst_acc_wr_control(devinfo, inst->raw) ||
(ARF == file &&
reg != BRW_ARF_NULL) ||
(ARF == inst->dst.file &&
@ -1680,8 +1680,8 @@ special_requirements_for_handling_double_precision_data_types(
*/
if (is_double_precision &&
intel_device_info_is_9lp(devinfo)) {
ERROR_IF(brw_inst_no_dd_check(devinfo, inst->raw) ||
brw_inst_no_dd_clear(devinfo, inst->raw),
ERROR_IF(brw_eu_inst_no_dd_check(devinfo, inst->raw) ||
brw_eu_inst_no_dd_clear(devinfo, inst->raw),
"DepCtrl is not allowed when the execution type is 64-bit");
}
@ -1795,7 +1795,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
}
if (inst->opcode == BRW_OPCODE_MATH) {
unsigned math_function = brw_inst_math_function(devinfo, inst->raw);
unsigned math_function = brw_eu_inst_math_function(devinfo, inst->raw);
switch (math_function) {
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:
@ -1969,7 +1969,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
}
if (inst->opcode == BRW_OPCODE_DPAS) {
ERROR_IF(brw_inst_dpas_3src_sdepth(devinfo, inst->raw) != BRW_SYSTOLIC_DEPTH_8,
ERROR_IF(brw_eu_inst_dpas_3src_sdepth(devinfo, inst->raw) != BRW_SYSTOLIC_DEPTH_8,
"Systolic depth must be 8.");
const unsigned sdepth = 8;
@ -1980,7 +1980,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
const enum brw_reg_type src2_type = inst->src[2].type;
const enum gfx12_sub_byte_precision src1_sub_byte =
brw_inst_dpas_3src_src1_subbyte(devinfo, inst->raw);
brw_eu_inst_dpas_3src_src1_subbyte(devinfo, inst->raw);
if (src1_type != BRW_TYPE_B && src1_type != BRW_TYPE_UB) {
ERROR_IF(src1_sub_byte != BRW_SUB_BYTE_PRECISION_NONE,
@ -1993,7 +1993,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
}
const enum gfx12_sub_byte_precision src2_sub_byte =
brw_inst_dpas_3src_src2_subbyte(devinfo, inst->raw);
brw_eu_inst_dpas_3src_src2_subbyte(devinfo, inst->raw);
if (src2_type != BRW_TYPE_B && src2_type != BRW_TYPE_UB) {
ERROR_IF(src2_sub_byte != BRW_SUB_BYTE_PRECISION_NONE,
@ -2007,11 +2007,11 @@ instruction_restrictions(const struct brw_isa_info *isa,
const unsigned src1_bits_per_element =
brw_type_size_bits(src1_type) >>
brw_inst_dpas_3src_src1_subbyte(devinfo, inst->raw);
brw_eu_inst_dpas_3src_src1_subbyte(devinfo, inst->raw);
const unsigned src2_bits_per_element =
brw_type_size_bits(src2_type) >>
brw_inst_dpas_3src_src2_subbyte(devinfo, inst->raw);
brw_eu_inst_dpas_3src_src2_subbyte(devinfo, inst->raw);
/* The MAX2(1, ...) is just to prevent possible division by 0 later. */
const unsigned ops_per_chan =
@ -2059,7 +2059,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
ERROR_IF((src2_subnr * brw_type_size_bytes(src2_type) * src2_bits_per_element) / 8 >= REG_SIZE,
"Src2 subregister specifies next register.");
if (brw_inst_3src_atomic_control(devinfo, inst->raw)) {
if (brw_eu_inst_3src_atomic_control(devinfo, inst->raw)) {
/* FINISHME: When we start emitting DPAS with Atomic set, figure out
* a way to validate it. Also add a test in test_eu_validate.cpp.
*/
@ -2068,7 +2068,7 @@ instruction_restrictions(const struct brw_isa_info *isa,
"DPAS instruction.");
}
if (brw_inst_dpas_3src_exec_type(devinfo, inst->raw) ==
if (brw_eu_inst_dpas_3src_exec_type(devinfo, inst->raw) ==
BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT) {
ERROR_IF(dst_type != BRW_TYPE_F,
"DPAS destination type must be F.");
@ -2124,7 +2124,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
if (inst_is_split_send(isa, inst)) {
/* We can only validate immediate descriptors */
if (brw_inst_send_sel_reg32_desc(devinfo, inst->raw))
if (brw_eu_inst_send_sel_reg32_desc(devinfo, inst->raw))
return error_msg;
} else if (inst_is_send(inst)) {
/* We can only validate immediate descriptors */
@ -2134,9 +2134,9 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
return error_msg;
}
const uint32_t desc = brw_inst_send_desc(devinfo, inst->raw);
const uint32_t desc = brw_eu_inst_send_desc(devinfo, inst->raw);
switch (brw_inst_sfid(devinfo, inst->raw)) {
switch (brw_eu_inst_sfid(devinfo, inst->raw)) {
case BRW_SFID_URB:
if (devinfo->ver < 20)
break;
@ -2156,11 +2156,11 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
break;
}
if (brw_inst_sfid(devinfo, inst->raw) == BRW_SFID_URB && devinfo->ver < 20) {
ERROR_IF(!brw_inst_header_present(devinfo, inst->raw),
if (brw_eu_inst_sfid(devinfo, inst->raw) == BRW_SFID_URB && devinfo->ver < 20) {
ERROR_IF(!brw_eu_inst_header_present(devinfo, inst->raw),
"Header must be present for all URB messages.");
switch (brw_inst_urb_opcode(devinfo, inst->raw)) {
switch (brw_eu_inst_urb_opcode(devinfo, inst->raw)) {
case GFX7_URB_OPCODE_ATOMIC_INC:
case GFX7_URB_OPCODE_ATOMIC_MOV:
case GFX8_URB_OPCODE_ATOMIC_ADD:
@ -2168,7 +2168,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
break;
case GFX8_URB_OPCODE_SIMD8_READ:
ERROR_IF(brw_inst_rlen(devinfo, inst->raw) == 0,
ERROR_IF(brw_eu_inst_rlen(devinfo, inst->raw) == 0,
"URB SIMD8 read message must read some data.");
break;
@ -2440,14 +2440,14 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
struct string error_msg = { .str = NULL, .len = 0 };
inst->raw = raw;
inst->opcode = brw_inst_opcode(isa, raw);
inst->opcode = brw_eu_inst_opcode(isa, raw);
inst->num_sources = brw_num_sources_from_inst(isa, raw);
const struct opcode_desc *desc = brw_opcode_desc(isa, inst->opcode);
assert(desc->ndst == 0 || desc->ndst == 1);
inst->has_dst = desc->ndst == 1;
enum brw_execution_size exec_size = brw_inst_exec_size(devinfo, raw);
enum brw_execution_size exec_size = brw_eu_inst_exec_size(devinfo, raw);
switch (exec_size) {
case BRW_EXECUTE_1:
case BRW_EXECUTE_2:
@ -2462,8 +2462,8 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
break;
}
inst->access_mode = brw_inst_access_mode(devinfo, raw);
inst->pred_control = brw_inst_pred_control(devinfo, raw);
inst->access_mode = brw_eu_inst_access_mode(devinfo, raw);
inst->pred_control = brw_eu_inst_pred_control(devinfo, raw);
RETURN_ERROR_IF(inst->num_sources == 3 && inst->access_mode == BRW_ALIGN_1 && devinfo->ver == 9,
"Align1 mode not allowed on Gfx9 for 3-src instructions");
@ -2529,67 +2529,67 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
inst->opcode == BRW_OPCODE_SYNC);
if (inst->has_dst) {
inst->dst.file = brw_inst_dst_reg_file(devinfo, raw);
inst->dst.type = brw_inst_dst_type(devinfo, raw);
inst->dst.address_mode = brw_inst_dst_address_mode(devinfo, raw);
inst->dst.file = brw_eu_inst_dst_reg_file(devinfo, raw);
inst->dst.type = brw_eu_inst_dst_type(devinfo, raw);
inst->dst.address_mode = brw_eu_inst_dst_address_mode(devinfo, raw);
if (inst->dst.address_mode == BRW_ADDRESS_DIRECT) {
inst->dst.nr = brw_inst_dst_da_reg_nr(devinfo, raw);
inst->dst.nr = brw_eu_inst_dst_da_reg_nr(devinfo, raw);
if (inst->access_mode == BRW_ALIGN_1) {
inst->dst.subnr = brw_inst_dst_da1_subreg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_dst_da1_subreg_nr(devinfo, raw);
} else {
inst->dst.subnr = brw_inst_dst_da16_subreg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_dst_da16_subreg_nr(devinfo, raw);
}
} else {
inst->dst.subnr = brw_inst_dst_ia_subreg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_dst_ia_subreg_nr(devinfo, raw);
}
inst->dst.hstride = STRIDE(brw_inst_dst_hstride(devinfo, raw));
inst->dst.hstride = STRIDE(brw_eu_inst_dst_hstride(devinfo, raw));
}
inst->src[0].file = brw_inst_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_inst_src0_type(devinfo, raw);
inst->src[0].address_mode = brw_inst_src0_address_mode(devinfo, raw);
inst->src[0].negate = brw_inst_src0_negate(devinfo, raw);
inst->src[0].abs = brw_inst_src0_abs(devinfo, raw);
inst->src[0].file = brw_eu_inst_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_eu_inst_src0_type(devinfo, raw);
inst->src[0].address_mode = brw_eu_inst_src0_address_mode(devinfo, raw);
inst->src[0].negate = brw_eu_inst_src0_negate(devinfo, raw);
inst->src[0].abs = brw_eu_inst_src0_abs(devinfo, raw);
if (inst->src[0].file != IMM) {
if (inst->src[0].address_mode == BRW_ADDRESS_DIRECT) {
inst->src[0].nr = brw_inst_src0_da_reg_nr(devinfo, raw);
inst->src[0].nr = brw_eu_inst_src0_da_reg_nr(devinfo, raw);
if (inst->access_mode == BRW_ALIGN_1) {
inst->src[0].subnr = brw_inst_src0_da1_subreg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_src0_da1_subreg_nr(devinfo, raw);
} else {
inst->src[0].subnr = brw_inst_src0_da16_subreg_nr(devinfo, raw) * 16;
inst->src[0].subnr = brw_eu_inst_src0_da16_subreg_nr(devinfo, raw) * 16;
}
} else {
inst->src[0].subnr = brw_inst_src0_ia_subreg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_src0_ia_subreg_nr(devinfo, raw);
}
inst->src[0].vstride = STRIDE(brw_inst_src0_vstride(devinfo, raw));
inst->src[0].vstride = STRIDE(brw_eu_inst_src0_vstride(devinfo, raw));
if (inst->access_mode == BRW_ALIGN_1) {
inst->src[0].width = WIDTH(brw_inst_src0_width(devinfo, raw));
inst->src[0].hstride = STRIDE(brw_inst_src0_hstride(devinfo, raw));
inst->src[0].width = WIDTH(brw_eu_inst_src0_width(devinfo, raw));
inst->src[0].hstride = STRIDE(brw_eu_inst_src0_hstride(devinfo, raw));
}
}
if (inst->num_sources > 1) {
inst->src[1].file = brw_inst_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_inst_src1_type(devinfo, raw);
inst->src[1].negate = brw_inst_src1_negate(devinfo, raw);
inst->src[1].abs = brw_inst_src1_abs(devinfo, raw);
inst->src[1].file = brw_eu_inst_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_eu_inst_src1_type(devinfo, raw);
inst->src[1].negate = brw_eu_inst_src1_negate(devinfo, raw);
inst->src[1].abs = brw_eu_inst_src1_abs(devinfo, raw);
if (inst->src[1].file != IMM) {
if (inst->src[1].address_mode == BRW_ADDRESS_DIRECT) {
inst->src[1].nr = brw_inst_src1_da_reg_nr(devinfo, raw);
inst->src[1].nr = brw_eu_inst_src1_da_reg_nr(devinfo, raw);
if (inst->access_mode == BRW_ALIGN_1) {
inst->src[1].subnr = brw_inst_src1_da1_subreg_nr(devinfo, raw);
inst->src[1].subnr = brw_eu_inst_src1_da1_subreg_nr(devinfo, raw);
} else {
inst->src[1].subnr = brw_inst_src1_da16_subreg_nr(devinfo, raw) * 16;
inst->src[1].subnr = brw_eu_inst_src1_da16_subreg_nr(devinfo, raw) * 16;
}
} else {
inst->src[1].subnr = brw_inst_src1_ia_subreg_nr(devinfo, raw);
inst->src[1].subnr = brw_eu_inst_src1_ia_subreg_nr(devinfo, raw);
}
inst->src[1].vstride = STRIDE(brw_inst_src1_vstride(devinfo, raw));
inst->src[1].vstride = STRIDE(brw_eu_inst_src1_vstride(devinfo, raw));
if (inst->access_mode == BRW_ALIGN_1) {
inst->src[1].width = WIDTH(brw_inst_src1_width(devinfo, raw));
inst->src[1].hstride = STRIDE(brw_inst_src1_hstride(devinfo, raw));
inst->src[1].width = WIDTH(brw_eu_inst_src1_width(devinfo, raw));
inst->src[1].hstride = STRIDE(brw_eu_inst_src1_hstride(devinfo, raw));
}
}
}
@ -2602,64 +2602,64 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
assert(inst->has_dst);
if (inst->access_mode == BRW_ALIGN_1) {
inst->dst.file = brw_inst_3src_a1_dst_reg_file(devinfo, raw);
inst->dst.type = brw_inst_3src_a1_dst_type(devinfo, raw);
inst->dst.nr = brw_inst_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_inst_3src_a1_dst_subreg_nr(devinfo, raw) * 8;
inst->dst.hstride = STRIDE(brw_inst_3src_a1_dst_hstride(devinfo, raw));
inst->dst.file = brw_eu_inst_3src_a1_dst_reg_file(devinfo, raw);
inst->dst.type = brw_eu_inst_3src_a1_dst_type(devinfo, raw);
inst->dst.nr = brw_eu_inst_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_3src_a1_dst_subreg_nr(devinfo, raw) * 8;
inst->dst.hstride = STRIDE(brw_eu_inst_3src_a1_dst_hstride(devinfo, raw));
inst->src[0].file = brw_inst_3src_a1_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_inst_3src_a1_src0_type(devinfo, raw);
inst->src[0].negate = brw_inst_3src_src0_negate(devinfo, raw);
inst->src[0].abs = brw_inst_3src_src0_abs(devinfo, raw);
inst->src[0].file = brw_eu_inst_3src_a1_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_eu_inst_3src_a1_src0_type(devinfo, raw);
inst->src[0].negate = brw_eu_inst_3src_src0_negate(devinfo, raw);
inst->src[0].abs = brw_eu_inst_3src_src0_abs(devinfo, raw);
if (inst->src[0].file != IMM) {
inst->src[0].nr = brw_inst_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_inst_3src_a1_src0_subreg_nr(devinfo, raw);
inst->src[0].vstride = VSTRIDE_3SRC(brw_inst_3src_a1_src0_vstride(devinfo, raw));
inst->src[0].hstride = STRIDE(brw_inst_3src_a1_src0_hstride(devinfo, raw));
inst->src[0].nr = brw_eu_inst_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_3src_a1_src0_subreg_nr(devinfo, raw);
inst->src[0].vstride = VSTRIDE_3SRC(brw_eu_inst_3src_a1_src0_vstride(devinfo, raw));
inst->src[0].hstride = STRIDE(brw_eu_inst_3src_a1_src0_hstride(devinfo, raw));
}
inst->src[1].file = brw_inst_3src_a1_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_inst_3src_a1_src1_type(devinfo, raw);
inst->src[1].negate = brw_inst_3src_src1_negate(devinfo, raw);
inst->src[1].abs = brw_inst_3src_src1_abs(devinfo, raw);
inst->src[1].nr = brw_inst_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_inst_3src_a1_src1_subreg_nr(devinfo, raw);
inst->src[1].vstride = VSTRIDE_3SRC(brw_inst_3src_a1_src1_vstride(devinfo, raw));
inst->src[1].hstride = STRIDE(brw_inst_3src_a1_src1_hstride(devinfo, raw));
inst->src[1].file = brw_eu_inst_3src_a1_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_eu_inst_3src_a1_src1_type(devinfo, raw);
inst->src[1].negate = brw_eu_inst_3src_src1_negate(devinfo, raw);
inst->src[1].abs = brw_eu_inst_3src_src1_abs(devinfo, raw);
inst->src[1].nr = brw_eu_inst_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_eu_inst_3src_a1_src1_subreg_nr(devinfo, raw);
inst->src[1].vstride = VSTRIDE_3SRC(brw_eu_inst_3src_a1_src1_vstride(devinfo, raw));
inst->src[1].hstride = STRIDE(brw_eu_inst_3src_a1_src1_hstride(devinfo, raw));
inst->src[2].file = brw_inst_3src_a1_src2_reg_file(devinfo, raw);
inst->src[2].type = brw_inst_3src_a1_src2_type(devinfo, raw);
inst->src[2].negate = brw_inst_3src_src2_negate(devinfo, raw);
inst->src[2].abs = brw_inst_3src_src2_abs(devinfo, raw);
inst->src[2].file = brw_eu_inst_3src_a1_src2_reg_file(devinfo, raw);
inst->src[2].type = brw_eu_inst_3src_a1_src2_type(devinfo, raw);
inst->src[2].negate = brw_eu_inst_3src_src2_negate(devinfo, raw);
inst->src[2].abs = brw_eu_inst_3src_src2_abs(devinfo, raw);
if (inst->src[2].file != IMM) {
inst->src[2].nr = brw_inst_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_inst_3src_a1_src2_subreg_nr(devinfo, raw);
inst->src[2].hstride = STRIDE(brw_inst_3src_a1_src2_hstride(devinfo, raw));
inst->src[2].nr = brw_eu_inst_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_eu_inst_3src_a1_src2_subreg_nr(devinfo, raw);
inst->src[2].hstride = STRIDE(brw_eu_inst_3src_a1_src2_hstride(devinfo, raw));
}
} else {
inst->dst.file = FIXED_GRF;
inst->dst.type = brw_inst_3src_a16_dst_type(devinfo, raw);
inst->dst.nr = brw_inst_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_inst_3src_a16_dst_subreg_nr(devinfo, raw) * 4;
inst->dst.type = brw_eu_inst_3src_a16_dst_type(devinfo, raw);
inst->dst.nr = brw_eu_inst_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_3src_a16_dst_subreg_nr(devinfo, raw) * 4;
enum brw_reg_type src_type = brw_inst_3src_a16_src_type(devinfo, raw);
enum brw_reg_type src_type = brw_eu_inst_3src_a16_src_type(devinfo, raw);
inst->src[0].file = FIXED_GRF;
inst->src[0].type = src_type;
inst->src[0].nr = brw_inst_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_inst_3src_a16_src0_subreg_nr(devinfo, raw) * 4;
inst->src[0].nr = brw_eu_inst_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_3src_a16_src0_subreg_nr(devinfo, raw) * 4;
inst->src[1].file = FIXED_GRF;
inst->src[1].type = src_type;
inst->src[1].nr = brw_inst_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_inst_3src_a16_src1_subreg_nr(devinfo, raw) * 4;
inst->src[1].nr = brw_eu_inst_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_eu_inst_3src_a16_src1_subreg_nr(devinfo, raw) * 4;
inst->src[2].file = FIXED_GRF;
inst->src[2].type = src_type;
inst->src[2].nr = brw_inst_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_inst_3src_a16_src2_subreg_nr(devinfo, raw) * 4;
inst->src[2].nr = brw_eu_inst_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_eu_inst_3src_a16_src2_subreg_nr(devinfo, raw) * 4;
}
break;
}
@ -2668,25 +2668,25 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
assert(inst->num_sources == 3);
assert(inst->has_dst);
inst->dst.file = brw_inst_dpas_3src_dst_reg_file(devinfo, raw);
inst->dst.type = brw_inst_dpas_3src_dst_type(devinfo, raw);
inst->dst.nr = brw_inst_dpas_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_inst_dpas_3src_dst_subreg_nr(devinfo, raw);
inst->dst.file = brw_eu_inst_dpas_3src_dst_reg_file(devinfo, raw);
inst->dst.type = brw_eu_inst_dpas_3src_dst_type(devinfo, raw);
inst->dst.nr = brw_eu_inst_dpas_3src_dst_reg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_dpas_3src_dst_subreg_nr(devinfo, raw);
inst->src[0].file = brw_inst_dpas_3src_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_inst_dpas_3src_src0_type(devinfo, raw);
inst->src[0].nr = brw_inst_dpas_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_inst_dpas_3src_src0_subreg_nr(devinfo, raw);
inst->src[0].file = brw_eu_inst_dpas_3src_src0_reg_file(devinfo, raw);
inst->src[0].type = brw_eu_inst_dpas_3src_src0_type(devinfo, raw);
inst->src[0].nr = brw_eu_inst_dpas_3src_src0_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_dpas_3src_src0_subreg_nr(devinfo, raw);
inst->src[1].file = brw_inst_dpas_3src_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_inst_dpas_3src_src1_type(devinfo, raw);
inst->src[1].nr = brw_inst_dpas_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_inst_dpas_3src_src1_subreg_nr(devinfo, raw);
inst->src[1].file = brw_eu_inst_dpas_3src_src1_reg_file(devinfo, raw);
inst->src[1].type = brw_eu_inst_dpas_3src_src1_type(devinfo, raw);
inst->src[1].nr = brw_eu_inst_dpas_3src_src1_reg_nr(devinfo, raw);
inst->src[1].subnr = brw_eu_inst_dpas_3src_src1_subreg_nr(devinfo, raw);
inst->src[2].file = brw_inst_dpas_3src_src2_reg_file(devinfo, raw);
inst->src[2].type = brw_inst_dpas_3src_src2_type(devinfo, raw);
inst->src[2].nr = brw_inst_dpas_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_inst_dpas_3src_src2_subreg_nr(devinfo, raw);
inst->src[2].file = brw_eu_inst_dpas_3src_src2_reg_file(devinfo, raw);
inst->src[2].type = brw_eu_inst_dpas_3src_src2_type(devinfo, raw);
inst->src[2].nr = brw_eu_inst_dpas_3src_src2_reg_nr(devinfo, raw);
inst->src[2].subnr = brw_eu_inst_dpas_3src_src2_subreg_nr(devinfo, raw);
break;
}
@ -2694,36 +2694,36 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
if (inst->opcode == BRW_OPCODE_SENDS || inst->opcode == BRW_OPCODE_SENDSC) {
assert(devinfo->ver < 12);
inst->dst.file = brw_inst_send_dst_reg_file(devinfo, raw);
inst->dst.file = brw_eu_inst_send_dst_reg_file(devinfo, raw);
inst->dst.type = BRW_TYPE_D;
inst->dst.nr = brw_inst_dst_da_reg_nr(devinfo, raw);
inst->dst.subnr = brw_inst_dst_da16_subreg_nr(devinfo, raw) * 16;
inst->dst.nr = brw_eu_inst_dst_da_reg_nr(devinfo, raw);
inst->dst.subnr = brw_eu_inst_dst_da16_subreg_nr(devinfo, raw) * 16;
inst->src[0].file = FIXED_GRF;
inst->src[0].type = BRW_TYPE_D;
inst->src[0].nr = brw_inst_src0_da_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_inst_src0_da16_subreg_nr(devinfo, raw) * 16;
inst->src[0].nr = brw_eu_inst_src0_da_reg_nr(devinfo, raw);
inst->src[0].subnr = brw_eu_inst_src0_da16_subreg_nr(devinfo, raw) * 16;
if (inst->num_sources > 1) {
inst->src[1].file = brw_inst_send_src1_reg_file(devinfo, raw);
inst->src[1].file = brw_eu_inst_send_src1_reg_file(devinfo, raw);
inst->src[1].type = BRW_TYPE_D;
inst->src[1].nr = brw_inst_send_src1_reg_nr(devinfo, raw);
inst->src[1].nr = brw_eu_inst_send_src1_reg_nr(devinfo, raw);
}
} else {
assert(devinfo->ver >= 12);
inst->dst.file = brw_inst_dst_reg_file(devinfo, raw);
inst->dst.file = brw_eu_inst_dst_reg_file(devinfo, raw);
inst->dst.type = BRW_TYPE_D;
inst->dst.nr = brw_inst_dst_da_reg_nr(devinfo, raw);
inst->dst.nr = brw_eu_inst_dst_da_reg_nr(devinfo, raw);
inst->src[0].file = brw_inst_send_src0_reg_file(devinfo, raw);
inst->src[0].file = brw_eu_inst_send_src0_reg_file(devinfo, raw);
inst->src[0].type = BRW_TYPE_D;
inst->src[0].nr = brw_inst_src0_da_reg_nr(devinfo, raw);
inst->src[0].nr = brw_eu_inst_src0_da_reg_nr(devinfo, raw);
if (inst->num_sources > 1) {
inst->src[1].file = brw_inst_send_src1_reg_file(devinfo, raw);
inst->src[1].file = brw_eu_inst_send_src1_reg_file(devinfo, raw);
inst->src[1].type = BRW_TYPE_D;
inst->src[1].nr = brw_inst_send_src1_reg_nr(devinfo, raw);
inst->src[1].nr = brw_eu_inst_send_src1_reg_nr(devinfo, raw);
}
}
break;
@ -2756,13 +2756,13 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
inst->format == FORMAT_BASIC_THREE_SRC ||
inst->format == FORMAT_DPAS_THREE_SRC) &&
!inst_is_send(inst)) {
inst->saturate = brw_inst_saturate(devinfo, raw);
inst->saturate = brw_eu_inst_saturate(devinfo, raw);
if (inst->num_sources > 1 ||
devinfo->ver < 12 ||
inst->src[0].file != IMM ||
brw_type_size_bytes(inst->src[0].type) < 8) {
inst->cond_modifier = brw_inst_cond_modifier(devinfo, raw);
inst->cond_modifier = brw_eu_inst_cond_modifier(devinfo, raw);
}
}
@ -2831,7 +2831,7 @@ brw_validate_instructions(const struct brw_isa_info *isa,
for (int src_offset = start_offset; src_offset < end_offset;) {
const brw_eu_inst *inst = assembly + src_offset;
bool is_compact = brw_inst_cmpt_control(devinfo, inst);
bool is_compact = brw_eu_inst_cmpt_control(devinfo, inst);
unsigned inst_size = is_compact ? sizeof(brw_eu_compact_inst)
: sizeof(brw_eu_inst);
brw_eu_inst uncompacted;

50
src/intel/compiler/brw_fs_generator.cpp
View file

@ -140,17 +140,17 @@ fs_generator::patch_halt_jumps()
* tests.
*/
brw_eu_inst *last_halt = brw_HALT(p);
brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
brw_eu_inst_set_uip(p->devinfo, last_halt, 1 * scale);
brw_eu_inst_set_jip(p->devinfo, last_halt, 1 * scale);
int ip = p->nr_insn;
foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
brw_eu_inst *patch = &p->store[patch_ip->ip];
assert(brw_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT);
assert(brw_eu_inst_opcode(p->isa, patch) == BRW_OPCODE_HALT);
/* HALT takes a half-instruction distance from the pre-incremented IP. */
brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
brw_eu_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
}
this->discard_halt_patches.make_empty();
@ -184,13 +184,13 @@ fs_generator::generate_send(fs_inst *inst,
inst->send_ex_desc_scratch,
inst->send_ex_bso, inst->eot);
if (inst->check_tdr)
brw_inst_set_opcode(p->isa, brw_last_inst,
brw_eu_inst_set_opcode(p->isa, brw_last_inst,
devinfo->ver >= 12 ? BRW_OPCODE_SENDC : BRW_OPCODE_SENDSC);
} else {
brw_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
inst->eot);
if (inst->check_tdr)
brw_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC);
brw_eu_inst_set_opcode(p->isa, brw_last_inst, BRW_OPCODE_SENDC);
}
}
@ -284,18 +284,18 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
* instruction.
*/
insn = brw_MOV(p, addr, brw_imm_uw(imm_byte_offset));
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
brw_eu_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_eu_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
brw_eu_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
insn = brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_regdist(1));
else
brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
brw_eu_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
if (brw_type_size_bytes(reg.type) > 4 &&
(intel_device_info_is_9lp(devinfo) || !devinfo->has_64bit_int)) {
@ -428,12 +428,12 @@ fs_generator::generate_shuffle(fs_inst *inst,
* pipelined NoMask MOV instruction.
*/
insn = brw_MOV(p, addr, brw_imm_uw(src_start_offset));
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
brw_eu_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
brw_eu_inst_set_pred_control(devinfo, insn, BRW_PREDICATE_NONE);
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
brw_eu_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
/* Take into account the component size and horizontal stride. */
assert(src.vstride == src.hstride + src.width);
@ -443,7 +443,7 @@ fs_generator::generate_shuffle(fs_inst *inst,
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_regdist(1));
else
brw_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
brw_eu_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
/* Add on the register start offset */
brw_ADD(p, addr, addr, brw_imm_uw(src_start_offset));
@ -513,8 +513,8 @@ fs_generator::generate_quad_swizzle(const fs_inst *inst,
stride(suboffset(src, BRW_GET_SWZ(swiz, c)), 4, 1, 0));
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(devinfo, insn, c < 3);
brw_inst_set_no_dd_check(devinfo, insn, c > 0);
brw_eu_inst_set_no_dd_clear(devinfo, insn, c < 3);
brw_eu_inst_set_no_dd_check(devinfo, insn, c > 0);
}
brw_set_default_swsb(p, tgl_swsb_null());
@ -716,22 +716,22 @@ fs_generator::generate_scratch_header(fs_inst *inst,
if (devinfo->ver >= 12)
brw_set_default_swsb(p, tgl_swsb_null());
else
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
brw_eu_inst_set_no_dd_clear(p->devinfo, insn, true);
/* Copy the per-thread scratch space size from g0.3[3:0] */
brw_set_default_exec_size(p, BRW_EXECUTE_1);
insn = brw_AND(p, suboffset(dst, 3), component(src, 3),
brw_imm_ud(INTEL_MASK(3, 0)));
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, insn, true);
brw_inst_set_no_dd_check(p->devinfo, insn, true);
brw_eu_inst_set_no_dd_clear(p->devinfo, insn, true);
brw_eu_inst_set_no_dd_check(p->devinfo, insn, true);
}
/* Copy the scratch base address from g0.5[31:10] */
insn = brw_AND(p, suboffset(dst, 5), component(src, 5),
brw_imm_ud(INTEL_MASK(31, 10)));
if (devinfo->ver < 12)
brw_inst_set_no_dd_check(p->devinfo, insn, true);
brw_eu_inst_set_no_dd_check(p->devinfo, insn, true);
}
void
@ -794,8 +794,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
*/
if (devinfo->ver <= 9 &&
p->nr_insn > 1 &&
brw_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH &&
brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
brw_eu_inst_opcode(p->isa, brw_last_inst) == BRW_OPCODE_MATH &&
brw_eu_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
inst->dst.component_size(inst->exec_size) > REG_SIZE) {
brw_NOP(p);
last_insn_offset = p->next_insn_offset;
@ -1375,10 +1375,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
brw_eu_inst *last = &p->store[last_insn_offset / 16];
if (inst->conditional_mod)
brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
brw_eu_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
if (devinfo->ver < 12) {
brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
brw_eu_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
brw_eu_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
}
}

186
src/intel/compiler/brw_gram.y
View file

@ -279,38 +279,38 @@ static void
i965_asm_set_instruction_options(struct brw_codegen *p,
struct options options)
{
brw_inst_set_access_mode(p->devinfo, brw_last_inst,
brw_eu_inst_set_access_mode(p->devinfo, brw_last_inst,
options.access_mode);
brw_inst_set_mask_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_mask_control(p->devinfo, brw_last_inst,
options.mask_control);
if (p->devinfo->ver < 12) {
brw_inst_set_thread_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_thread_control(p->devinfo, brw_last_inst,
options.thread_control);
brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
brw_eu_inst_set_no_dd_check(p->devinfo, brw_last_inst,
options.no_dd_check);
brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
brw_eu_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
options.no_dd_clear);
} else {
enum opcode opcode = brw_inst_opcode(p->isa, brw_last_inst);
brw_inst_set_swsb(p->devinfo, brw_last_inst,
enum opcode opcode = brw_eu_inst_opcode(p->isa, brw_last_inst);
brw_eu_inst_set_swsb(p->devinfo, brw_last_inst,
tgl_swsb_encode(p->devinfo, options.depinfo,
opcode));
}
brw_inst_set_debug_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_debug_control(p->devinfo, brw_last_inst,
options.debug_control);
if (brw_has_branch_ctrl(p->devinfo, brw_inst_opcode(p->isa, brw_last_inst))) {
if (brw_has_branch_ctrl(p->devinfo, brw_eu_inst_opcode(p->isa, brw_last_inst))) {
if (options.acc_wr_control)
error(NULL, "Instruction does not support AccWrEnable\n");
brw_inst_set_branch_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_branch_control(p->devinfo, brw_last_inst,
options.branch_control);
} else if (options.branch_control) {
error(NULL, "Instruction does not support BranchCtrl\n");
} else if (p->devinfo->ver < 20) {
brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
options.acc_wr_control);
}
brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
brw_eu_inst_set_cmpt_control(p->devinfo, brw_last_inst,
options.compaction);
}
@ -661,7 +661,7 @@ illegalinstruction:
ILLEGAL execsize instoptions
{
brw_next_insn(p, $1);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
i965_asm_set_instruction_options(p, $3);
}
;
@ -674,25 +674,25 @@ unaryinstruction:
i965_asm_unary_instruction($2, p, $6, $7);
brw_pop_insn_state(p);
i965_asm_set_instruction_options(p, $8);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
brw_eu_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_inst_set_flag_reg_nr(p->devinfo,
if (!brw_eu_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_eu_inst_set_flag_reg_nr(p->devinfo,
brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_flag_subreg_nr(p->devinfo,
brw_eu_inst_set_flag_subreg_nr(p->devinfo,
brw_last_inst,
$4.flag_subreg_nr);
}
if ($7.file != IMM) {
brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
brw_eu_inst_set_src0_vstride(p->devinfo, brw_last_inst,
$7.vstride);
}
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_inst_set_group(p->devinfo, brw_last_inst, $8.chan_offset);
brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $8.chan_offset);
}
;
@ -719,19 +719,19 @@ binaryinstruction:
brw_set_default_access_mode(p, $9.access_mode);
i965_asm_binary_instruction($2, p, $6, $7, $8);
i965_asm_set_instruction_options(p, $9);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
brw_eu_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
if (!brw_eu_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_eu_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
brw_eu_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
$4.flag_subreg_nr);
}
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_pop_insn_state(p);
}
@ -762,21 +762,21 @@ binaryaccinstruction:
i965_asm_binary_instruction($2, p, $6, $7, $8);
brw_pop_insn_state(p);
i965_asm_set_instruction_options(p, $9);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
brw_eu_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_inst_set_flag_reg_nr(p->devinfo,
if (!brw_eu_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
brw_eu_inst_set_flag_reg_nr(p->devinfo,
brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_flag_subreg_nr(p->devinfo,
brw_eu_inst_set_flag_subreg_nr(p->devinfo,
brw_last_inst,
$4.flag_subreg_nr);
}
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
}
;
@ -801,9 +801,9 @@ mathinstruction:
brw_set_default_access_mode(p, $9.access_mode);
gfx6_math(p, $6, $4, $7, $8);
i965_asm_set_instruction_options(p, $9);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_pop_insn_state(p);
}
;
@ -842,19 +842,19 @@ ternaryinstruction:
i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
brw_pop_insn_state(p);
i965_asm_set_instruction_options(p, $10);
brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
brw_eu_inst_set_cond_modifier(p->devinfo, brw_last_inst,
$4.cond_modifier);
if (p->devinfo->ver < 12) {
brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
brw_eu_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
$4.flag_reg_nr);
brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
brw_eu_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
$4.flag_subreg_nr);
}
brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_inst_set_group(p->devinfo, brw_last_inst, $10.chan_offset);
brw_eu_inst_set_saturate(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $10.chan_offset);
}
;
@ -874,7 +874,7 @@ waitinstruction:
{
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $4);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_set_default_access_mode(p, $4.access_mode);
struct brw_reg dest = $3;
dest.swizzle = brw_swizzle_for_mask(dest.writemask);
@ -883,7 +883,7 @@ waitinstruction:
brw_set_dest(p, brw_last_inst, dest);
brw_set_src0(p, brw_last_inst, dest);
brw_set_src1(p, brw_last_inst, brw_null_reg());
brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
brw_eu_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
}
;
@ -892,16 +892,16 @@ sendinstruction:
predicate sendopcode execsize dst payload exp2 sharedfunction msgdesc instoptions
{
i965_asm_set_instruction_options(p, $9);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $5);
brw_eu_inst_set_bits(brw_last_inst, 127, 96, $6);
brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
brw_eu_inst_set_src1_file_type(p->devinfo, brw_last_inst,
IMM,
BRW_TYPE_UD);
brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
brw_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_eu_inst_set_sfid(p->devinfo, brw_last_inst, $7);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $9.chan_offset);
brw_pop_insn_state(p);
}
@ -910,46 +910,46 @@ sendinstruction:
assert(p->devinfo->ver < 12);
i965_asm_set_instruction_options(p, $10);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $5);
brw_eu_inst_set_bits(brw_last_inst, 127, 96, $7);
brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
brw_inst_set_group(p->devinfo, brw_last_inst, $10.chan_offset);
brw_eu_inst_set_sfid(p->devinfo, brw_last_inst, $8);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $10.chan_offset);
brw_pop_insn_state(p);
}
| predicate sendsopcode execsize dst payload payload desc ex_desc sharedfunction msgdesc instoptions
{
i965_asm_set_instruction_options(p, $11);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $5);
brw_set_src1(p, brw_last_inst, $6);
if ($7.file == IMM) {
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0);
brw_inst_set_send_desc(p->devinfo, brw_last_inst, $7.ud);
brw_eu_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0);
brw_eu_inst_set_send_desc(p->devinfo, brw_last_inst, $7.ud);
} else {
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
}
if ($8.file == IMM) {
brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0);
brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8.ud, false);
brw_eu_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0);
brw_eu_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8.ud, false);
} else {
brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1);
brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $8.subnr >> 2);
brw_eu_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $8.subnr >> 2);
}
brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
brw_inst_set_eot(p->devinfo, brw_last_inst, $11.end_of_thread);
brw_inst_set_group(p->devinfo, brw_last_inst, $11.chan_offset);
brw_eu_inst_set_sfid(p->devinfo, brw_last_inst, $9);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $11.end_of_thread);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $11.chan_offset);
if (p->devinfo->verx10 >= 125 && $10.ex_bso) {
brw_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1);
brw_inst_set_send_src1_len(p->devinfo, brw_last_inst,
brw_eu_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_src1_len(p->devinfo, brw_last_inst,
$10.src1_len);
}
@ -960,32 +960,32 @@ sendinstruction:
assert(p->devinfo->ver >= 30);
i965_asm_set_instruction_options(p, $13);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $7);
brw_set_src1(p, brw_last_inst, brw_null_reg());
if ($9.file == IMM) {
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0);
brw_inst_set_send_desc(p->devinfo, brw_last_inst, $9.ud);
brw_eu_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 0);
brw_eu_inst_set_send_desc(p->devinfo, brw_last_inst, $9.ud);
} else {
brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
}
if ($10.file == IMM) {
brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0);
brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $10.ud, true);
brw_eu_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 0);
brw_eu_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $10.ud, true);
} else {
brw_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1);
brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $10.subnr >> 2);
brw_eu_inst_set_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $10.subnr >> 2);
}
brw_inst_set_sfid(p->devinfo, brw_last_inst, $11);
brw_inst_set_eot(p->devinfo, brw_last_inst, $13.end_of_thread);
brw_inst_set_group(p->devinfo, brw_last_inst, $13.chan_offset);
brw_eu_inst_set_sfid(p->devinfo, brw_last_inst, $11);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $13.end_of_thread);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $13.chan_offset);
if ($12.ex_bso) {
brw_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1);
brw_eu_inst_set_send_ex_bso(p->devinfo, brw_last_inst, 1);
/* Not settings src1 length, as its implied zero. */
}
@ -1069,12 +1069,12 @@ jumpinstruction:
{
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_ip_reg());
brw_set_src1(p, brw_last_inst, $4);
brw_inst_set_pred_control(p->devinfo, brw_last_inst,
brw_inst_pred_control(p->devinfo,
brw_eu_inst_set_pred_control(p->devinfo, brw_last_inst,
brw_eu_inst_pred_control(p->devinfo,
brw_last_inst));
brw_pop_insn_state(p);
}
@ -1088,7 +1088,7 @@ branchinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1101,7 +1101,7 @@ branchinstruction:
brw_next_insn(p, $1);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_TYPE_D));
@ -1115,7 +1115,7 @@ branchinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst,
vec1(retype(brw_null_reg(),
@ -1136,7 +1136,7 @@ breakinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_TYPE_D));
@ -1151,7 +1151,7 @@ breakinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
BRW_TYPE_D));
@ -1169,7 +1169,7 @@ breakinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst, brw_ip_reg());
brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
@ -1186,7 +1186,7 @@ loopinstruction:
brw_next_insn(p, $2);
i965_asm_set_instruction_options(p, $5);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
brw_set_dest(p, brw_last_inst,
retype(brw_null_reg(),
@ -1219,10 +1219,10 @@ syncinstruction:
brw_set_default_access_mode(p, $6.access_mode);
brw_SYNC(p, $3);
i965_asm_set_instruction_options(p, $6);
brw_inst_set_exec_size(p->devinfo, brw_last_inst, $4);
brw_eu_inst_set_exec_size(p->devinfo, brw_last_inst, $4);
brw_set_src0(p, brw_last_inst, $5);
brw_inst_set_eot(p->devinfo, brw_last_inst, $6.end_of_thread);
brw_inst_set_group(p->devinfo, brw_last_inst, $6.chan_offset);
brw_eu_inst_set_eot(p->devinfo, brw_last_inst, $6.end_of_thread);
brw_eu_inst_set_group(p->devinfo, brw_last_inst, $6.chan_offset);
brw_pop_insn_state(p);
}

20
src/intel/compiler/test_eu_compact.cpp
View file

@ -95,10 +95,10 @@ clear_pad_bits(const struct brw_isa_info *isa, brw_eu_inst *inst)
{
const struct intel_device_info *devinfo = isa->devinfo;
if (brw_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
brw_inst_src0_reg_file(devinfo, inst) != IMM &&
brw_inst_src1_reg_file(devinfo, inst) != IMM) {
if (brw_eu_inst_opcode(isa, inst) != BRW_OPCODE_SEND &&
brw_eu_inst_opcode(isa, inst) != BRW_OPCODE_SENDC &&
brw_eu_inst_src0_reg_file(devinfo, inst) != IMM &&
brw_eu_inst_src1_reg_file(devinfo, inst) != IMM) {
brw_eu_inst_set_bits(inst, 127, 111, 0);
}
}
@ -116,7 +116,7 @@ skip_bit(const struct brw_isa_info *isa, brw_eu_inst *src, int bit)
if (bit == 29)
return true;
if (is_3src(isa, brw_inst_opcode(isa, src))) {
if (is_3src(isa, brw_eu_inst_opcode(isa, src))) {
if (bit == 127)
return true;
} else {
@ -131,10 +131,10 @@ skip_bit(const struct brw_isa_info *isa, brw_eu_inst *src, int bit)
}
/* sometimes these are pad bits. */
if (brw_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
brw_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
brw_inst_src0_reg_file(devinfo, src) != IMM &&
brw_inst_src1_reg_file(devinfo, src) != IMM &&
if (brw_eu_inst_opcode(isa, src) != BRW_OPCODE_SEND &&
brw_eu_inst_opcode(isa, src) != BRW_OPCODE_SENDC &&
brw_eu_inst_src0_reg_file(devinfo, src) != IMM &&
brw_eu_inst_src1_reg_file(devinfo, src) != IMM &&
bit >= 121) {
return true;
}
@ -285,6 +285,6 @@ TEST_P(Instructions, f0_1_MOV_GRF_GRF)
brw_push_insn_state(p);
brw_set_default_predicate_control(p, BRW_PREDICATE_NORMAL);
brw_eu_inst *mov = brw_MOV(p, g0, g2);
brw_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
brw_eu_inst_set_flag_subreg_nr(p->devinfo, mov, 1);
brw_pop_insn_state(p);
}

642
src/intel/compiler/test_eu_validate.cpp
View file

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