Commit graph

73537 commits

Author SHA1 Message Date
Grazvydas Ignotas
e4fc06a2f8 util: add MAYBE_UNUSED for config dependent variables
This is mostly for variables that are only used in asserts and cause
unused-but-set-variable warnings in release builds. Could just use
UNUSED directly, but MAYBE_UNUSED should be less confusing and is
similar to what the Linux kernel has.

And yes __attribute__((unused)) can be used on variables on both GCC 4.2
(oldest supported by mesa) and clang 3.0 (just some random old version,
not sure what's the minimum for mesa).

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-04-25 12:23:10 +02:00
Hans de Goede
787a53988c nouveau: codegen: combineLd/St do not combine indirect loads
combineLd/St would combine, i.e. :

st  u32 # g[$r2+0x0] $r2
st  u32 # g[$r2+0x4] $r3

into:

st  u64 # g[$r2+0x0] $r2d

But this is only valid if r2 contains an 8 byte aligned address,
which is not guaranteed for compute shaders

This commit checks for src0 dim 0 not being indirect when combining
loads / stores as combining indirect loads / stores may break alignment
rules.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-04-25 11:45:07 +02:00
Rob Clark
0831eb94b9 freedreno/ir3: relax restriction in grouping
Currently we were two restrictive, and would insert an output move in
cases like: MOV OUT[0], IN[0].xyzw

Loosen the restriction to allow the current instruction to appear in the
neighbor list but only at it's current possition.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
36c9ea6e79 freedreno/ir3: fix small memory leak
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
610837fb98 freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always.  For
example, in a sam(w) which only writes the 4th component.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
adf795432f freedreno/a4xx: better workaround for astc+srgb
This *seems* like a hw bug, and maybe only applies to certain a4xx
variants/revisions.  But setting the SRGB bit in sampler view state
(texconst0) causes invalid alpha for ASTC textures.  Work around this
setting up a second texture state and using that to sample alpha
separately.

This way, srgb->linear conversion happens in hw *prior* to
interpolation.

This fixes 546 dEQP tests: dEQP-GLES3.functional.texture.*astc*srgb*

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Rob Clark
a148300b13 Revert "freedreno/a4xx: lower srgb in shader for astc textures"
Better workaround in the following patch.

This reverts commit 899bd63ace.
2016-04-24 13:40:57 -04:00
Rob Clark
19118e6f47 freedreno/a4xx: blend state no longer depends on fb state
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-24 13:40:57 -04:00
Marek Olšák
c0c6ca40a2 Revert "st/dri: add 32-bit RGBX/RGBA formats"
This reverts commit ccdcf91104.

It breaks most KDE apps, because DRI doesn't support the RGBA component
ordering.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95071
2016-04-24 15:16:07 +02:00
Jonathan Gray
147a2d25ad genxml: use PYTHON3
Allows the build to work when the python3 binary is not "python3".

v2: remove x bit from the script at Emil's suggestion

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 16:45:05 -07:00
Nanley Chery
710b1d2e66 i965/tex_image: Flush certain subnormal ASTC channel values
When uploading a linear, void-extent, ASTC LDR block on Skylake, we are
required to flush to zero the UNORM16 channel values that would be
denormalized. This is specifically required for the values: 1, 2, and 3.

Fixes the 14 failing tests in:
   dEQP-GLES3.functional.texture.compressed.astc.void_extent_ldr.*

v2: Split out flushing function (Kristian Høgsberg)
v3: Map with READ instead of INVALIDATE (Kenneth Graunke)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 11:35:08 -07:00
Topi Pohjolainen
f8dd07a2c3 i965/blorp: Enable for buffer resolves
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:29:15 +03:00
Topi Pohjolainen
c7cf17ae75 i965/blorp: Enable for normal color clears
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:29:15 +03:00
Topi Pohjolainen
c4ec0121a8 i965/blorp: Fix clear code for ignoring colormask for XRGB formats on Gen9+
This is equivalent of 73b01e2711
for blorp.

v2 (Ken): No need to call _mesa_format_has_color_component() now
          that the number of components is gotten from
          _mesa_base_format_component_count().

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:29:15 +03:00
Topi Pohjolainen
19948f1bf6 mesa/formats: Take luminance into account in component count
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2016-04-23 07:29:15 +03:00
Topi Pohjolainen
9e153c0692 i965/blorp: Do not trigger re-emission of base state address
In case blorp needs to configure it will be just as if render or
compute pipeline had configured it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:28:58 +03:00
Topi Pohjolainen
84db9ca3f7 i965/blorp: Reconfigure base state address only if needed
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:09:39 +03:00
Topi Pohjolainen
234b5f23f8 i965/blorp: Use BRW_NEW_BLORP instead of trashing all state bits
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:09:39 +03:00
Kenneth Graunke
6d5ce1b043 i965: Make all atoms to track BRW_NEW_BLORP by default
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com
2016-04-23 07:09:39 +03:00
Topi Pohjolainen
65a5af6dd0 i965: Introduce state flag for blorp
In the past, BLORP has clobbered all BRW_NEW_* state flags, to trigger
re-emission of the entire 3D pipeline on the next draw.  However, there
are some packets BLORP simply leaves alone, so there's no need to
re-emit them.  Trying to reduce the set of dirty bits flagged after
BLORP runs is tricky.

Instead, we introduce a BRW_NEW_BLORP flag.  This should be set on any
atom which emits a packet that BLORP also emits.  When BLORP runs, it
will flag BRW_NEW_BLORP, causing those packets to get re-emitted.

This also makes it easy to avoid re-emitting specific atoms - we can
simply drop the BRW_NEW_BLORP flag on those.

To start, we assume that all packets need to be re-emitted.  This is the
safest approach and closest to the existing code's behavior.  Many of
these are obviously not required, and can be dropped in subsequent
patches.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:09:39 +03:00
Topi Pohjolainen
0e850452d1 i965/blorp/gen6: Use normal base state address setup
This is identical to the blorp version which only differs in case
fragment shader isn't used. In that case blorp would reset batch
buffer address to zero.
This is not really needed, and having blorp to use base state
address setup that is compatible with normal upload allows one to
skip resetting it.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:09:39 +03:00
Topi Pohjolainen
ae73e86497 i965: Remove pointers to non-existing atoms
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-23 07:09:39 +03:00
Tom Stellard
9f110a9e10 radeonsi: Implement ddx/ddy on VI using ds_bpermute
The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads.  These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.

DDX BEFORE:                        |  DDX AFTER:
                                   |
v_mbcnt_lo_u32_b32_e64 v2, -1, 0   |  v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2  |  v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2        |  v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2           |  v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2        |  ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1                   |  ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0                |  s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0)               |
v_or_b32_e32 v0, 1, v2             |
v_lshlrev_b32_e32 v0, 2, v0        |
ds_read_b32 v1, v3                 |
ds_read_b32 v0, v0                 |
s_waitcnt lgkmcnt(0)               |
                                   |
LDS: 1 blocks                      |  LDS: 0 blocks

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:43 +00:00
Tom Stellard
128267d781 radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid
We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.

v2:
  - Only do this with LLVM 3.8 and newer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:43 +00:00
Tom Stellard
d3427412a3 radeonsi: Set range metadata on calls to llvm.SI.tid
The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:48:41 +00:00
Tom Stellard
b31422d970 radeonsi: Create a helper function for computing the thread id
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-22 23:45:34 +00:00
Nanley Chery
86cd9a134f i965: Disable KHR_texture_compression_astc_hdr on Gen9
Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.

With this change, we are no longer failing the 14 tests from:
   dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-22 16:57:38 -07:00
Tim Rowley
ec089cd987 swr: [rasterizer memory] Constify load tiles
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:49:20 -05:00
Tim Rowley
6facf4b74a swr: [rasterizer core] CompleteDrawContext changes for gcc
Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:49:04 -05:00
Tim Rowley
0487377dce swr: [rasterizer] Small cleanups
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:56 -05:00
Tim Rowley
2c4c3c9c71 swr: [rasterizer scripts] Knob scripts tweaks
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:47 -05:00
Tim Rowley
ef293ee9c0 swr: [rasterizer] Interpolation utility functions
v2: use _mm_cmpunord_ps for vIsNaN

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:38 -05:00
Tim Rowley
27cc5924ea swr: [rasterizer core] TemplateArgUnroller
Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.

This allows the template argument unroller to easily be extended to enums.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:29 -05:00
Tim Rowley
46a448d161 swr: [rasterizer core] Arena: make most allocated blocks the same size
Reduces sorting cost

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:20 -05:00
Tim Rowley
794be41f91 swr: [rasterizer core] Fix global arena allocator bug
- Plus some minor code refactoring

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:48:11 -05:00
Tim Rowley
e42f00ee39 swr: [rasterizer core] Fix thread binding for 32-bit windows
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:59 -05:00
Tim Rowley
cd21f90ecf swr: [rasterizer fetch] Add support for fetching non-uniform component formats
For example, R10G10B10A2_UNORM.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:48 -05:00
Tim Rowley
244ae7af1b swr: [rasterizer core] Use CS spill/fill size in core
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:47:02 -05:00
Tim Rowley
ee9621e2f5 swr: fix memory leaks from vs/fs compilation
v2: varient -> variant

Reviewed by: George Kyriazis <George.Kyriazis@intel.com>
2016-04-22 18:05:02 -05:00
Tim Rowley
5815c8b3d3 swr: fix clang warnings
v2: use alternate logic version in swr_check_render_cond

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2016-04-22 18:03:41 -05:00
Rob Clark
e85bef8b12 freedreno/a4xx: fix encoding of blend color state
Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now
they all pass)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-22 15:00:34 -04:00
Rob Clark
23abc41d2b freedreno: update generated headers
Pull in RB_BLEND_* fixes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-04-22 15:00:34 -04:00
Eric Anholt
79b36168e0 vc4: Make sure we recompile when sample_mask changes.
Part of fixing piglit EXT_framebuffer_multisample/sample-coverage inverted
(there is also a bug with RCL tiled blits)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-22 11:27:11 -07:00
Eric Anholt
876c647194 vc4: Fix validation of full res tile offset if used for non-MSAA.
There's no reason we couldn't do non-MSAA full resolution tile buffer
load/stores, but we would have claimed buffer overflow was being
attempted.  Nothing does this currently.
2016-04-22 11:27:11 -07:00
Eric Anholt
3fecaf0d0c vc4: Only do MSAA FB operations if the FB is MSAA.
I noticed this as a problem with ET:QW traces emitting coverage code when
the framebuffer was supposed to be single sampled.
2016-04-22 11:27:11 -07:00
Eric Anholt
1410403e1e vc4: Fix tests for format supported with nr_samples == 1.
This was a bug from the MSAA enabling.  Tests for surfaces with
nr_samples==1 instead of 0 (generally GL renderbuffers) would incorrectly
fail out.

Fixes the ARB_framebuffer_sRGB piglit tests other than srgb_conformance.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-22 11:27:11 -07:00
Eric Anholt
6eabdb8959 vc4: Don't try to blit from MSAA surfaces with mismatched width to dst.
I had made the previous blit fix non-MSAA only because I was thinking
about how the hardware infers stride from the RENDERING_CONFIG packet.
However, I'm also inferring the stride for both MSAA src and dst in
vc4_render_cl.c from the width argument in the ioctl.

Fixes 15 EXT_framebuffer_multisample piglit tests.
2016-04-22 11:27:11 -07:00
Kenneth Graunke
42dea145d9 i965: Disable channel expressions for scalar GS, TCS, TES.
On Broadwell, I get the following shader-db statistics:

Tessellation Control Shaders:

   total instructions in shared programs: 57327 -> 57012 (-0.55%)
   instructions in affected programs: 27334 -> 27019 (-1.15%)
   helped: 45
   HURT: 0

   total cycles in shared programs: 265692 -> 255188 (-3.95%)
   cycles in affected programs: 263122 -> 252618 (-3.99%)
   helped: 184
   HURT: 26

Tessellation Evaluation Shaders:

   total instructions in shared programs: 23236 -> 23157 (-0.34%)
   instructions in affected programs: 2791 -> 2712 (-2.83%)
   helped: 27
   HURT: 0

   total cycles in shared programs: 151858 -> 149704 (-1.42%)
   cycles in affected programs: 151858 -> 149704 (-1.42%)
   helped: 101
   HURT: 114

Geometry Shaders:

   Orbital Explorer goes from 6442 -> 6356 instructions.
   Two Shadow of Mordor shaders increase by a single instruction.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-04-22 10:26:30 -07:00
Topi Pohjolainen
1883613a24 i965/blorp: Add support for 2x msaa
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-22 17:02:29 +03:00
Topi Pohjolainen
125a7fdf32 i965/blorp: Add support for encoding/decoding interleaved 2x msaa
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-04-22 17:01:29 +03:00