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vc4: Don't try to blit from MSAA surfaces with mismatched width to dst.

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I had made the previous blit fix non-MSAA only because I was thinking
about how the hardware infers stride from the RENDERING_CONFIG packet.
However, I'm also inferring the stride for both MSAA src and dst in
vc4_render_cl.c from the width argument in the ioctl.

Fixes 15 EXT_framebuffer_multisample piglit tests.
This commit is contained in:
Eric Anholt 2016-04-20 14:11:04 -07:00
parent 42dea145d9
commit 6eabdb8959
1 changed files with 14 additions and 11 deletions
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25
src/gallium/drivers/vc4/vc4_blit.c
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@ -93,20 +93,23 @@ vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
* destination surface) to determine the stride. This may be wrong
* when reading from texture miplevels > 0, which are stored in
* POT-sized areas. For MSAA, the tile addresses are computed
* explicitly by the RCL.
* explicitly by the RCL, but still use the destination width to
* determine the stride (which could be fixed by explicitly supplying
* it in the ABI).
*/
if (info->src.resource->nr_samples <= 1) {
struct vc4_resource *rsc = vc4_resource(info->src.resource);
struct vc4_resource *rsc = vc4_resource(info->src.resource);
uint32_t stride = dst_surface_width * rsc->cpp;
if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T)
stride = align(stride, 128);
else
stride = align(stride, 16);
uint32_t stride;
if (stride != rsc->slices[info->src.level].stride)
return false;
}
if (info->src.resource->nr_samples > 1)
stride = align(dst_surface_width, 32) * 4 * rsc->cpp;
else if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T)
stride = align(dst_surface_width * rsc->cpp, 128);
else
stride = align(dst_surface_width * rsc->cpp, 16);
if (stride != rsc->slices[info->src.level].stride)
return false;
if (info->dst.resource->format != info->src.resource->format)
return false;