mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-06 05:08:08 +02:00
freedreno/ir3: fix small RA bug
Normally the offset in the group would be the same, but not always. For example, in a sam(w) which only writes the 4th component. Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
parent
adf795432f
commit
610837fb98
1 changed files with 2 additions and 1 deletions
|
|
@ -469,7 +469,8 @@ get_definer(struct ir3_ra_ctx *ctx, struct ir3_instruction *instr,
|
|||
|
||||
*sz = MAX2(*sz, dsz);
|
||||
|
||||
/* Fanout's are grouped, so *off should already valid */
|
||||
debug_assert(instr->opc == OPC_META_FO);
|
||||
*off = MAX2(*off, instr->fo.off);
|
||||
|
||||
d = dd;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue