Commit graph

9469 commits

Author SHA1 Message Date
Samuel Pitoiset
b7d21220e8 radv/rmv: fix logging sparse residency
The offset should be the sparse image/buffer offset.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28367>
2024-03-27 08:52:50 +01:00
Samuel Pitoiset
13ad10bd26 radv/rmv: fix logging of per-queue destroyed BOs
They should be logged before actually destroyed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28367>
2024-03-27 08:52:50 +01:00
Samuel Pitoiset
3f0e1aae87 radv/rmv: add missing logging when events are destroyed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28367>
2024-03-27 08:52:50 +01:00
Samuel Pitoiset
d004c2e725 radv/rmv: add missing logging when sparse BOs are destroyed
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28367>
2024-03-27 08:52:50 +01:00
Samuel Pitoiset
328f74fb44 radv: make sure to disable NGG culling with TES when the FS stage is unknown
NGG culling depends on the number of FS input reads but this can be
unknown with GPL/ESO when VS/TES are compiled separately. While VS
has a prolog most of the time, TES might incorrectly enable NGG culling
because the number of FS inputs was considered to be zero. To fix that,
consider the number of FS input reads to be the maximum possible value
when the FS is unknown to implicitly disable NGG culling.

This fixes a bunch of tess related flakes with Zink/ESO/RADV on RDNA2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28293>
2024-03-25 11:48:58 +00:00
Samuel Pitoiset
585b4c5a01 radv: invalidate L2 metadata for VK_ACCESS_2_MEMORY_READ_BIT
When shaders might read metadata (DCC) this must be flushed.
VK_ACCESS_2_MEMORY_READ_BIT includes all READ bits that are relevant.

I think this issue has been uncoverd since vkd3d-proton d1425ee4
("vkd3d: Use VK_ACCESS_MEMORY_{READ,WRITE}_BIT where appropriate")
because RADV used to be missing VK_ACCESS_2_MEMORY_{READ,WRITE} in the
past and vkd3d-proton added a special workaround that has been removed.

This fixes some DCC corruption in WWE 2K24.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10774
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28332>
2024-03-25 07:27:46 +00:00
Dave Airlie
4fc2ab43c0 radv/video: fix h265 decode with unaligned w/h
This is similiar to the h264 fix done previously.

Fixes decoding with the nvpro samples app and a test video.

Fixes: db62c38091 ("radv: add vcn h265 decode.")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28359>
2024-03-25 05:51:43 +00:00
Samuel Pitoiset
f729fe50e5 radv: trigger a new PS epilog when the framebuffer is dirty with ESO
When a new framebuffer is used, the color output formats might have
changed and a new PS epilog might need to be recompiled. This shouldn't
affect graphics pipeline because color output formats must already match.

This fixes a couple of failures/flakes like
spec@ext_framebuffer_multisample@fast-clear with Zink and shader object.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28294>
2024-03-22 15:08:23 +00:00
Samuel Pitoiset
53ec57d42d radv: always export MRTZ in FS epilogs with ESO on GFX11
Alpha to coverage is special on RDNA3 and it needs to be emitted
through MRTZ in some situations. Because we can't know this at compile
time when everything is dynamic, we have to always emit MRTZ in PS
epilogs.

This fixes remaining failures on NAVI31 with Zink/ESO/RADV like
spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-drawpixels-float-and-ushort.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28297>
2024-03-22 14:42:21 +00:00
Patrick Lerda
0fd907fc7b ac/llvm,radeonsi: fix memory leaks triggered by ac_nir_translate() errors
For instance, this issue is triggered with
"piglit/bin/glslparsertest tests/spec/arb_bindless_texture/compiler/images/arith-bound-image.frag pass 3.30 GL_ARB_bindless_texture GL_ARB_shader_image_load_store":
Direct leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe9a7 in calloc (/usr/lib64/libasan.so.6+0xb19a7)
    #1 0x7f84ba7e0801 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4391
    #2 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #3 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #4 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #5 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #6 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #7 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #8 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Direct leak of 136 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbff57 in operator new(unsigned long) (/usr/lib64/libasan.so.6+0xb2f57)
    #1 0x7f84b1a5f749 in LLVMCreateBuilderInContext (/usr/local/lib64/libLLVM-17.so+0xc84749)
    #2 0x7f84ba7817b0 in ac_llvm_context_init ../src/amd/llvm/ac_llvm_build.c:54
    #3 0x7f84ba542b7a in si_llvm_context_init ../src/gallium/drivers/radeonsi/si_shader_llvm.c:120
    #4 0x7f84ba542b7a in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:832
    #5 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #6 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #7 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #8 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #9 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
    #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
    #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
    #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
    #6 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
    #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #13 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 176 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b9fee in rzalloc_size ../src/util/ralloc.c:152
    #3 0x7f84b81b9fee in rzalloc_array_size ../src/util/ralloc.c:232
    #4 0x7f84b81b05c7 in _mesa_hash_table_init ../src/util/hash_table.c:163
    #5 0x7f84b81b05c7 in _mesa_hash_table_create ../src/util/hash_table.c:186
    #6 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
    #7 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #8 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #9 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #10 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #11 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #12 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #13 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 128 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
    #3 0x7f84ba7e06e4 in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4382
    #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #10 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

Indirect leak of 128 byte(s) in 1 object(s) allocated from:
    #0 0x7f84c3fbe7ef in __interceptor_malloc (/usr/lib64/libasan.so.6+0xb17ef)
    #1 0x7f84b81b9b3f in ralloc_size ../src/util/ralloc.c:118
    #2 0x7f84b81b046c in _mesa_hash_table_create ../src/util/hash_table.c:182
    #3 0x7f84ba7e06ae in ac_nir_translate ../src/amd/llvm/ac_nir_to_llvm.c:4381
    #4 0x7f84ba53fdf4 in si_llvm_translate_nir ../src/gallium/drivers/radeonsi/si_shader_llvm.c:759
    #5 0x7f84ba542bb7 in si_llvm_compile_shader ../src/gallium/drivers/radeonsi/si_shader_llvm.c:836
    #6 0x7f84ba337b8e in si_compile_shader ../src/gallium/drivers/radeonsi/si_shader.c:2874
    #7 0x7f84ba43a7c1 in si_init_shader_selector_async ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:3176
    #8 0x7f84b81c3448 in util_queue_thread_func ../src/util/u_queue.c:309
    #9 0x7f84b821ea6a in impl_thrd_routine ../src/c11/impl/threads_posix.c:67
    #10 0x7f84c2fea38a  (/lib64/libc.so.6+0x8438a)

SUMMARY: AddressSanitizer: 920 byte(s) leaked in 6 allocation(s).

Fixes: d92d35c9db ("ac/llvm: add a return value to ac_nir_translate")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28099>
2024-03-21 00:51:19 +00:00
Samuel Pitoiset
be4a6b946a radv: add a workaround for null IBO on GFX6
Based on PAL.

Fixes dEQP-VK.draw.*nulldescriptor_maintenance_5_maintenance6 on GFX6.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28263>
2024-03-20 16:27:58 +00:00
Konstantin Seurer
a6b93c50d0 radv/printf: Use fprintf instead of printf
For using other destinations than stdout.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28228>
2024-03-19 19:05:25 +00:00
Konstantin Seurer
d902b6d805 radv: Skip more acceleration structure build markers
We should skip even more stuff when using updates only.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28228>
2024-03-19 19:05:25 +00:00
Konstantin Seurer
6095b70f85 radv/rt: Use 32-bit offsets for load_sbt_entry
Totals from 82 (18.06% of 454) affected shaders:
MaxWaves: 820 -> 821 (+0.12%)
Instrs: 2765694 -> 2766338 (+0.02%); split: -0.08%, +0.10%
CodeSize: 14751988 -> 14735464 (-0.11%); split: -0.13%, +0.01%
VGPRs: 8464 -> 8448 (-0.19%)
SpillSGPRs: 454 -> 512 (+12.78%)
Latency: 19368679 -> 19344967 (-0.12%); split: -0.21%, +0.09%
InvThroughput: 5354427 -> 5346317 (-0.15%); split: -0.24%, +0.08%
VClause: 100183 -> 100331 (+0.15%); split: -0.02%, +0.17%
SClause: 66584 -> 66590 (+0.01%); split: -0.02%, +0.03%
Copies: 237008 -> 238684 (+0.71%); split: -0.53%, +1.23%
Branches: 113344 -> 113386 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 6141 -> 6194 (+0.86%)
PreVGPRs: 7916 -> 7880 (-0.45%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27725>
2024-03-19 17:03:28 +00:00
Konstantin Seurer
00dec03438 radv: Use radv_buffer_map for parsing IBs
We need matching pointers pointers for annotations to work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:14 +00:00
Konstantin Seurer
1d747653d4 radv: Add an IB annotation layer
The layer annotates the command buffers with api
entrypoint names.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:14 +00:00
Konstantin Seurer
8f0ee3a92b radv: Add support for IB annotations
Wires up ac_parse_ib annotation support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:14 +00:00
Konstantin Seurer
0f436e0fe1 ac/parse_ib: Replace the parameter list with ac_ib_parser
It's more code but it should be more readable. This also makes adding
optional arguments easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:13 +00:00
Konstantin Seurer
2e4d365104 ac: Annotate context rolls
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
2024-03-19 16:08:13 +00:00
Timur Kristóf
8f3cc3cb29 radv: Use mapped driver locations for determining I/O strides.
This will allow us to more accurately determine the
input and output strides, because the I/O locations mapped
by RADV don't match the locations in NIR.
As a result, ESO will use less LDS.

It also fixes the per-patch output stride of tess control
shaders, because previously we omitted tess factors from them.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
2024-03-19 15:01:19 +00:00
Timur Kristóf
2f1f55cf32 radv: Extract input and output stride info to new functions.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
2024-03-19 15:01:19 +00:00
Samuel Pitoiset
4d4b1820ca radv: add radv_force_pstate_peak_gfx11_dgpu and enable it for Helldivers 2
This seems to definitely improve stability issues (random GPU hangs)
with Helldivers 2 on RDNA3 dGPUs. RDNA3 APUs and other generations
shouldn't be affected.

This is a workaround.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10584
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28260>
2024-03-19 09:06:43 +00:00
Samuel Pitoiset
9b089ca943 radv: fix occlusion queries with MSAA and no attachments
The number of samples should be the rasterization samples and not the
framebuffer samples.

Fixes recent dEQP-VK.query_pool.occlusion_query.no_attachments_*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28198>
2024-03-19 07:19:07 +00:00
David Rosca
4b7b185711 radv/video: Set maxActiveReferencePictures to 16 for H264/5
H265 supports 16 reference frames too.

Fixes validation errors when decoding H265 stream with more than 8 reference
frames.

Cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27541>
2024-03-18 10:04:52 +00:00
Samuel Pitoiset
67fd490fe5 radv: add a GPU hang workaround for legacy tess+GS for GFX10.3
Ported from RadeonSI ea94cb95e4
("radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS")

Fixes: a23802bcb9 ("ac,radeonsi: start adding support for gfx10.3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15 16:38:14 +00:00
Samuel Pitoiset
96e9c3fe77 radv: program SAMPLE_MASK_TRACKER_WATERMARK optimally for GFX11 APUs
Ported from RadeonSI 6ce3a95852
("radeonsi/gfx11: program SAMPLE_MASK_TRACKER_WATERMARK optimally for APUs")

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15 16:38:14 +00:00
Samuel Pitoiset
d81809618f radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11
Ported from RadeonSI 7d3a414662
("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT")

Fixes: 25a66477d0 ("radeonsi/gfx11: register changes")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15 16:38:14 +00:00
Samuel Pitoiset
8203284c03 radv: disable binning correctly on GFX11.5
Ported from RadeonSI 20445f296b
("radeonsi: disable binning correctly on gfx11.5").

Fixes: b44a886b84 ("amd/common: add registers for gfx11.5")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
2024-03-15 16:38:14 +00:00
Samuel Pitoiset
6146a1651a radv: emit VGT_GS_OUT_PRIM_TYPE as part of the dynamic primitive topology
With pipelines, the topology class is known at creation time but with
ESO this needs to be re-emitted when the topology change and not only
when graphics shaders are emitted.

This fixes spec@nv_primitive_restart@primitive-restart-* with Zink
when shader object is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28179>
2024-03-15 09:26:33 +00:00
Samuel Pitoiset
ccf894f29c radv: fix RADV_PERFTEST=dmashaders with ESO
Update the shader upload sequence when individual shaders are bound
to fix that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28154>
2024-03-15 08:10:59 +00:00
Samuel Pitoiset
dd0b4f05ad radv: add helpers to bind the GS copy shader and the RT prolog
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28154>
2024-03-15 08:10:59 +00:00
Friedrich Vock
cc61409ea6 radv: Only enable SEs that the device reports
Matches PAL behavior.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28195>
2024-03-15 07:31:34 +00:00
Rhys Perry
df7024bcdd radv,aco: allow VS prologs to increase VGPR usage
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
2024-03-14 15:30:12 +00:00
Samuel Pitoiset
1a20942f6a radv: fix wave32 support with ESO
For example when RADV_PERFTEST=gewave32 is used, the vgt shader key
was incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
2024-03-14 14:56:45 +00:00
Samuel Pitoiset
e1c73db01c radv: rework generating vgt_shader_key for pipelines
This new helper will also be used for ESO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
2024-03-14 14:56:45 +00:00
Samuel Pitoiset
c6485f560d radv: determine radv_vgt_shader_key::has_ngg_xxx with the last VGT shader
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
2024-03-14 14:56:44 +00:00
Samuel Pitoiset
9ccbd459c6 radv: fix determining if PrimId is used for merged shaders compiled separately
For ESO when TES and GS are compiled separately,
BREAK_WAVE_AT_EOI/IA_SWITCH_ON_EOI must be enabled if the GS uses
PrimID.

This fixes
tests/spec/arb_tessellation_shader/execution/gs-primitiveid-instanced.shader_test
on RDNA2 when shader object is enabled with Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28149>
2024-03-14 14:34:19 +00:00
Lynne
ee476f3eda radv/av1: limit profile and bit depth to supported values
Same as with other codecs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28143>
2024-03-13 02:20:59 +00:00
Alyssa Rosenzweig
a6123a80da nir/opt_shrink_vectors: shrink some intrinsics from start
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.

v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.

RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)

AGX:

total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)

total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)

total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)

total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)

total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
2024-03-12 18:17:17 +00:00
Rhys Perry
a977a51a21 radv: stop using 5/8 component SSBO stores
These apparently work, but I'm not sure they were supposed to.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
2024-03-12 17:23:29 +00:00
Rhys Perry
cc7e3efc7c radv: don't advertise DGC with LLVM
The meta shaders for this feature don't compile with LLVM because of 5/8
component SSBO stores. I'm not sure this was ever expected to work.

This seemed to break vkd3d-proton.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
2024-03-12 17:23:29 +00:00
Friedrich Vock
4c35828933 radv,driconf: Remove active accel struct workaround
Now unused and enabled by default.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28077>
2024-03-11 17:08:09 +00:00
Friedrich Vock
217072d25f radv/rt: Force active leaves for every updateable accel struct
We can't rely on games getting updates right. To avoid adding
workarounds for tons of games, be more robust by default.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28077>
2024-03-11 17:08:09 +00:00
Samuel Pitoiset
898f28f790 radv: allow RADV_PERFTEST=shader_object on all GFX9 GPUs
Renoir used to hangs in CI but it's fixed now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28069>
2024-03-11 09:45:58 +00:00
Samuel Pitoiset
c7202751ad radv: fix emitting default blend state for PS without epilogs and ESO
When a fragment shader doesn't have any written color outputs it
doesn't need a PS epilog because it's unnecessary. Though, with ESO
the driver still needs to emit the default blend state like graphics
pipelines.

This fixes a bunch of flakes with ESO and Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28008>
2024-03-11 08:51:47 +00:00
Samuel Pitoiset
7ebff681db radv: re-emit RB+ state with PS epilogs only when the col format changes
RB+ was re-emitted every time a new PS epilog was requested even if
the non-compacted color format was equal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28008>
2024-03-11 08:51:47 +00:00
Samuel Pitoiset
c1307184d2 radv: stop using the custom blend mode for PS epilogs
Internal operations that set the custom blend mode are monolithic
pipelines only, and the value should always be zero.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28008>
2024-03-11 08:51:47 +00:00
Yiwei Zhang
c9d3cc2615 vulkan: refactor the runtime header gen order dependency
Summary:
- ensure headers used outside runtime are included in dependency source
- drop redundant idep_vulkan_common_entrypoints_h
- drop redundant icd side tricks for the order of header gen

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28066>
2024-03-08 21:42:07 +00:00
Yiwei Zhang
872c9fabeb vulkan: remove unused wsi_common_entrypoints include and dep
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28066>
2024-03-08 21:42:07 +00:00
Samuel Pitoiset
3f8ff988fa radv: add a helper to emit PS/TCS epilogs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28042>
2024-03-08 07:28:47 +00:00