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radv: emit VGT_GS_OUT_PRIM_TYPE as part of the dynamic primitive topology

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With pipelines, the topology class is known at creation time but with
ESO this needs to be re-emitted when the topology change and not only
when graphics shaders are emitted.

This fixes spec@nv_primitive_restart@primitive-restart-* with Zink
when shader object is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28179>
This commit is contained in:
Samuel Pitoiset 2024-03-14 14:29:24 +01:00 • committed by Marge Bot
parent ccf894f29c
commit 6146a1651a
2 changed files with 11 additions and 5 deletions
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12
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1944,11 +1944,13 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
radv_rast_prim_is_points_or_lines(pipeline->rast_prim))
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_GUARDBAND;
if (cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.dirty |=
RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY | RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading ||
cmd_buffer->state.emitted_graphics_pipeline->uses_out_of_order_rast != pipeline->uses_out_of_order_rast ||
cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment ||
cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim)
cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES;
if (cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable) {
@ -2316,6 +2318,7 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_shader *last_vgt_shader = cmd_buffer->state.last_vgt_shader;
const struct radv_userdata_info *loc = radv_get_user_sgpr(last_vgt_shader, AC_UD_NUM_VERTS_PER_PRIM);
const uint32_t vgt_gs_out_prim_type = radv_get_rasterization_prim(cmd_buffer);
const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
uint32_t base_reg;
@ -2328,6 +2331,8 @@ radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)
radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, d->vk.ia.primitive_topology);
}
radv_emit_vgt_gs_out(cmd_buffer->device, cmd_buffer->cs, vgt_gs_out_prim_type);
if (loc->sgpr_idx == -1)
return;
@ -9196,7 +9201,6 @@ radv_emit_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
radv_emit_vgt_gs_mode(device, cs, last_vgt_shader);
radv_emit_vgt_vertex_reuse(device, cs, radv_get_shader(cmd_buffer->state.shaders, MESA_SHADER_TESS_EVAL));
radv_emit_vgt_shader_config(device, cs, &vgt_shader_cfg_key);
radv_emit_vgt_gs_out(device, cs, radv_get_rasterization_prim(cmd_buffer));
if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX10_3) {
gfx103_emit_vgt_draw_payload_cntl(cs, cmd_buffer->state.shaders[MESA_SHADER_MESH], false);

4
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -3375,6 +3375,7 @@ radv_emit_mesh_shader(const struct radv_device *device, struct radeon_cmdbuf *ct
const struct radv_shader *ms)
{
const struct radv_physical_device *pdevice = device->physical_device;
const uint32_t gs_out = radv_conv_gl_prim_to_gs_out(ms->info.ms.output_prim);
radv_emit_hw_ngg(device, ctx_cs, cs, NULL, ms);
radeon_set_context_reg(
@ -3391,6 +3392,8 @@ radv_emit_mesh_shader(const struct radv_device *device, struct radeon_cmdbuf *ct
radeon_emit(cs, S_00B2B4_MAX_EXP_VERTS(ms->info.ngg_info.max_out_verts) |
S_00B2B4_MAX_EXP_PRIMS(ms->info.ngg_info.prim_amp_factor));
}
radv_emit_vgt_gs_out(device, ctx_cs, gs_out);
}
static uint32_t
@ -3799,7 +3802,6 @@ radv_pipeline_emit_pm4(const struct radv_device *device, struct radv_graphics_pi
radv_emit_vgt_vertex_reuse(device, ctx_cs, radv_get_shader(pipeline->base.shaders, MESA_SHADER_TESS_EVAL));
radv_emit_vgt_shader_config(device, ctx_cs, &vgt_shader_key);
radv_emit_vgt_gs_out(device, ctx_cs, vgt_gs_out_prim_type);
if (pdevice->rad_info.gfx_level >= GFX10_3) {
const bool enable_vrs = radv_is_vrs_enabled(pipeline, state);