amd/common: add registers for gfx11.5

Built from amd-staging-drm-next c5a7d38c2c7fc + Alex D
"drm/amdgpu: update to the latest GC 11.5 header" patch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25278>

src/amd/common/meson.build

@@ -29,6 +29,7 @@ amd_json_files = [
   '../registers/gfx10.json',
   '../registers/gfx103.json',
   '../registers/gfx11.json',
+  '../registers/gfx115.json',
 
   # Manually written:
   '../registers/pkt3.json',

src/amd/registers/makeregheader.py

@@ -32,6 +32,7 @@ CHIPS = [
     Object(name='gfx10', disambiguation='GFX10'),
     Object(name='gfx103', disambiguation='GFX103'),
     Object(name='gfx11', disambiguation='GFX11'),
+    Object(name='gfx115', disambiguation='GFX115'),
 ]
 
 ######### END HARDCODED CONFIGURATION

src/amd/registers/parse_kernel_headers.py

@@ -60,6 +60,12 @@ gfx_levels = {
         'asic_reg/gc/gc_11_0_0_sh_mask.h',
         'soc21_enum.h',
     ],
+    'gfx115': [
+        [0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0], # IP_BASE GC_BASE
+        'asic_reg/gc/gc_11_5_0_offset.h',
+        'asic_reg/gc/gc_11_5_0_sh_mask.h',
+        'soc21_enum.h',
+    ],
 }
 
 # match: #define mmSDMA0_DEC_START                              0x0000
@@ -698,6 +704,9 @@ enums_missing = {
   'gfx11': {
     **missing_enums_gfx11plus,
   },
+  'gfx115': {
+    **missing_enums_gfx11plus,
+  },
 }
 
 # Register field definitions that are missing in kernel headers