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radv: add a helper to emit PS/TCS epilogs

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28042>
This commit is contained in:
Samuel Pitoiset 2024-03-07 13:26:19 +01:00 • committed by Marge Bot
parent 0ed6aba85a
commit 3f8ff988fa
1 changed files with 21 additions and 22 deletions
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43
src/amd/vulkan/radv_cmd_buffer.c
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@ -1849,6 +1849,25 @@ radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_RBPLUS;
}
static void
radv_emit_epilog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *shader,
const struct radv_shader_part *epilog)
{
const struct radv_device *device = cmd_buffer->device;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
radv_cs_add_buffer(device->ws, cs, epilog->bo);
assert((epilog->va >> 32) == device->physical_device->rad_info.address32_hi);
const struct radv_userdata_info *loc = &shader->info.user_sgprs_locs.shader_data[AC_UD_EPILOG_PC];
const uint32_t base_reg = shader->info.user_data_0;
assert(loc->sgpr_idx != -1 && loc->num_sgprs == 1);
radv_emit_shader_pointer(device, cs, base_reg + loc->sgpr_idx * 4, epilog->va, false);
cmd_buffer->shader_upload_seq = MAX2(cmd_buffer->shader_upload_seq, epilog->upload_seq);
}
static void
radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader_part *ps_epilog)
{
@ -1878,17 +1897,7 @@ radv_emit_ps_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shader
radeon_set_sh_reg(cmd_buffer->cs, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
}
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, ps_epilog->bo);
assert((ps_epilog->va >> 32) == cmd_buffer->device->physical_device->rad_info.address32_hi);
struct radv_userdata_info *loc = &ps_shader->info.user_sgprs_locs.shader_data[AC_UD_EPILOG_PC];
uint32_t base_reg = ps_shader->info.user_data_0;
assert(loc->sgpr_idx != -1);
assert(loc->num_sgprs == 1);
radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ps_epilog->va, false);
cmd_buffer->shader_upload_seq = MAX2(cmd_buffer->shader_upload_seq, ps_epilog->upload_seq);
radv_emit_epilog(cmd_buffer, ps_shader, ps_epilog);
cmd_buffer->state.emitted_ps_epilog = ps_epilog;
}
@ -1917,17 +1926,7 @@ radv_emit_tcs_epilog_state(struct radv_cmd_buffer *cmd_buffer, struct radv_shade
radeon_set_sh_reg(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, rsrc1);
radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, tcs_epilog->bo);
assert((tcs_epilog->va >> 32) == cmd_buffer->device->physical_device->rad_info.address32_hi);
struct radv_userdata_info *loc = &tcs->info.user_sgprs_locs.shader_data[AC_UD_EPILOG_PC];
uint32_t base_reg = tcs->info.user_data_0;
assert(loc->sgpr_idx != -1);
assert(loc->num_sgprs == 1);
radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, tcs_epilog->va, false);
cmd_buffer->shader_upload_seq = MAX2(cmd_buffer->shader_upload_seq, tcs_epilog->upload_seq);
radv_emit_epilog(cmd_buffer, tcs, tcs_epilog);
cmd_buffer->state.emitted_tcs_epilog = tcs_epilog;
}