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radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11

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Ported from RadeonSI 7d3a414662
("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT")

Fixes: 25a66477d0 ("radeonsi/gfx11: register changes")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
This commit is contained in:
Samuel Pitoiset 2024-03-14 08:22:39 +01:00 • committed by Marge Bot
parent 8203284c03
commit d81809618f
1 changed files with 7 additions and 2 deletions
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9
src/amd/vulkan/si_cmd_buffer.c
View file

@ -514,9 +514,14 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
}
if (physical_device->rad_info.gfx_level >= GFX9) {
unsigned max_alloc_count = physical_device->rad_info.pbb_max_alloc_count;
/* GFX11+ shouldn't subtract 1 from pbb_max_alloc_count. */
if (physical_device->rad_info.gfx_level < GFX11)
max_alloc_count -= 1;
radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
S_028C48_MAX_ALLOC_COUNT(max_alloc_count) | S_028C48_MAX_PRIM_PER_BATCH(1023));
radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
}