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Author SHA1 Message Date
Samuel Pitoiset
ccde8ecd64 radv: compute the TMA BO size instead of using a constant 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
3e88f996a5 radv: fix the TMA descriptor size 
The TMA BO contains the descriptor first.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
6ec0c85908 radv,aco: use the trap handler layout struct while compiling the shader 
It's less error prone to rely on the layout for offsets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
6bfd92123f aco: simplify postprocessing the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
44dfeb4479 radv,aco: add a separate function to compile the trap handler shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
62e335c779 radv,aco: dump more SQ_WAVE regs from the trap handler 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Samuel Pitoiset
0cc21d0601 radv: cleanup printing SGPRS dumped from the trap handler 
It's more readable like that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>
 2024-11-12 11:16:13 +00:00
Georg Lehmann
ee74b090db nir/opt_16bit_tex_image: optimize extract half sources 
I also tried extract_i16/u16, but that causes a lot of regressions.

Foz-DB Navi21:
Totals from 3 (0.00% of 79395) affected shaders:
Instrs: 367 -> 355 (-3.27%)
CodeSize: 2156 -> 2136 (-0.93%)
VGPRs: 80 -> 72 (-10.00%)
Latency: 3163 -> 3153 (-0.32%); split: -0.51%, +0.19%
InvThroughput: 424 -> 404 (-4.72%)
Copies: 31 -> 42 (+35.48%); split: -3.23%, +38.71%
PreVGPRs: 27 -> 25 (-7.41%)
VALU: 208 -> 196 (-5.77%)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32058>
 2024-11-12 10:19:40 +00:00
Mary Guillemard
bad38c1e76 panvk: Implement global priority extensions 
Wire up with common kmod code.

On JM, this is a no-op implementation only allowing medium priority.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31961>
 2024-11-12 08:46:22 +00:00
Mary Guillemard
e2c81380a9 pan/kmod: Expose medium priority on panfrost 
Panfrost currently doesn't support priorities, assumes default priority as
medium to properly support global priorities on Vulkan.

Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31961>
 2024-11-12 08:46:22 +00:00
Mary Guillemard
2237cff1af panfrost: Report default value for GROUP_PRIORITIES_INFO in drm-shim 
Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31961>
 2024-11-12 08:46:22 +00:00
Zan Dobersek
25b73dff5a tu/a7xx: use concurrent resolve groups 
Establish groups of resolve and unresolve operations that the a7xx
hardware can then use to improve efficiency. Creating such groups enables
continuation of command stream processing while these (un)resolves are in
progress, as long as those latter operations don't depend on the grouped
(un)resolves.

To enable concurrent resolves and unresolves, corresponding fields on the
RB_CCU_CNTL register have to be set appropriately.

Resolve groups are tracked through a scoped struct that logs any pending
resolve operation. Once the group is complete, the emit helper function
will write out the CCU_END_RESOLVE_GROUP event to the command stream.

The buffer ID field on the RB_BLIT_INFO register can be used to disperse
different resolve operations across all available slots in the resolve
engine. The 0x8 and 0x9 IDs are reserved for depth and stencil buffers,
while the 0x0-0x7 range is used for color buffers. A simple incremented
counter is used to assign IDs for all color buffers inside any resolve
group. While it can occur for two color or depth/stencil buffers inside
the same resolve group to have identical IDs, hardware doesn't seem to
have a problem with handling that.

Two TU_DEBUG options are provided, 'noconcurrentresolves' and
'noconcurrentunresolves` disable respective operations by adjusting the
mode set through RB_CCU_CNTL.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31190>
 2024-11-12 07:50:45 +00:00
Zan Dobersek
f0e5331b21 freedreno/registers: update RB_BLIT_INFO, RB_CCU_CNTL 
For RB_BLIT_INFO, documentation of the buffer ID field is updated to
explain its use on a7xx.

RB_CCU_CNTL definition for a7xx is updated with fields for concurrent
resolve/unresolve modes and enhanced with dedicated enum types.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31190>
 2024-11-12 07:50:45 +00:00
Job Noorman
b36a7ce0f1 ir3/ra: prevent moving source intervals for shared collects 
Non-trivial collects (i.e., ones that will introduce moves because the
sources don't line-up with the destination) may cause source intervals
to get implicitly moved when they are inserted as children of the
destination interval. Since we don't support moving intervals in shared
RA, this may cause illegal register allocations. Prevent this by
creating a new top-level interval for the destination so that the source
intervals will be left alone.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fa22b0901a ("ir3/ra: Add specialized shared register RA/spilling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31978>
 2024-11-11 20:08:34 +00:00
Matt Turner
a2c4a34303 anv: Align anv_descriptor_pool::host_mem 
Otherwise anv_descriptor_set is accessed through an unaligned pointer,
which is undefined behavior in C.

```
anv_descriptor_set.c:1620:17: runtime error: member access within misaligned address 0x61900002c2b5
               for type 'struct anv_descriptor_set', which requires 8 byte alignment 0x61900002c2b5
```

Fixes: 2570a58bcd ("anv: Implement descriptor pools")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32070>
 2024-11-11 19:45:14 +00:00
Georg Lehmann
ece1ab3b87 radv: run copy prop before vectorizing 
Otherwise there are a lot of scalar movs between texture instructions
and alu. With those removed, the top down vectorizer has more starting
points.

Totals from 296 (0.37% of 79206) affected shaders:
MaxWaves: 5710 -> 5754 (+0.77%)
Instrs: 388051 -> 386630 (-0.37%); split: -0.46%, +0.09%
CodeSize: 2120800 -> 2117144 (-0.17%); split: -0.30%, +0.13%
VGPRs: 17496 -> 17344 (-0.87%)
Latency: 8893751 -> 8901364 (+0.09%); split: -0.10%, +0.18%
InvThroughput: 1740411 -> 1731710 (-0.50%); split: -0.57%, +0.07%
VClause: 6573 -> 6576 (+0.05%); split: -0.21%, +0.26%
SClause: 11233 -> 11209 (-0.21%); split: -0.28%, +0.07%
Copies: 31582 -> 31635 (+0.17%); split: -1.49%, +1.66%
PreSGPRs: 15878 -> 15876 (-0.01%)
PreVGPRs: 15380 -> 15274 (-0.69%)
VALU: 278528 -> 277036 (-0.54%); split: -0.65%, +0.11%
SALU: 49062 -> 49054 (-0.02%); split: -0.03%, +0.02%

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32060>
 2024-11-11 18:33:48 +00:00
Samuel Pitoiset
107f29c39a aco: do not reorder s_trap instructions 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32055>
 2024-11-11 15:46:36 +00:00
Asahi Lina
252e9a4cdf hk: Bump up max buffer size 
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Asahi Lina
81546c769e asahi: Use 64bit size fields 
This allows for BOs >4G.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
63dd4c13d0 asahi: move agx_gather_device_key 
for precomp

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
7e57e0aa7d asahi: factor out more compiled shader 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
f36ea1818b asahi: drop dead param 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
e7f100013f asahi: don't take compiled_shader in agx_build_internal_usc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
8d73a3ae40 asahi: assert/cse resource valid 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
b94bcf0318 asahi: fix a2c with sample shading, harder 
Fixes: 9bbe93d158 ("hk: fix alpha-to-coverage with sample shading")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
b9429930b9 asahi: correct core count, max freq 
fixes clinfo.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
beab5d2792 asahi: extract agx_get_num_cores 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
e145425746 agx: fuse also 8-bit address math 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
75d3c51e51 libagx: drop silliness in restart kernel 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
4660911cf9 libagx: fix unroll kernel constant qualifier 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
2963cd900f libagx: don't key unroll to index size 
Probably a premature optimization, it's annoying for precomp and for DGC.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
6030b204d5 libagx: simplify index patch expression 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
5e4e8df95a libagx: drop Clockwise 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
0c0097ab34 libagx: vectorize triangle def'n 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
c54fdde1a4 libagx: drop dead code 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
d00a504cb0 libagx: drop branch 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
28a2844309 libagx: fix cl warning 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
663b367a76 hk: fix meta shader name 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
f8b69ebdc2 hk: drop assert 
works fine without.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
ece3bd74db agx: make imad+ishl rules actually work 
total instructions in shared programs: 2750211 -> 2750184 (<.01%)
instructions in affected programs: 50499 -> 50472 (-0.05%)
helped: 27
HURT: 0
Instructions are helped.

total alu in shared programs: 2273669 -> 2273642 (<.01%)
alu in affected programs: 29874 -> 29847 (-0.09%)
helped: 27
HURT: 0
Alu are helped.

total fscib in shared programs: 2271986 -> 2271959 (<.01%)
fscib in affected programs: 29874 -> 29847 (-0.09%)
helped: 27
HURT: 0
Fscib are helped.

total bytes in shared programs: 21475184 -> 21474968 (<.01%)
bytes in affected programs: 371574 -> 371358 (-0.06%)
helped: 27
HURT: 0
Bytes are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
f737470736 agx: fuse iadd+large shift into imad 
total instructions in shared programs: 2750352 -> 2750211 (<.01%)
instructions in affected programs: 86944 -> 86803 (-0.16%)
helped: 32
HURT: 18
Instructions are helped.

total alu in shared programs: 2273810 -> 2273669 (<.01%)
alu in affected programs: 76720 -> 76579 (-0.18%)
helped: 32
HURT: 18
Alu are helped.

total fscib in shared programs: 2272127 -> 2271986 (<.01%)
fscib in affected programs: 76720 -> 76579 (-0.18%)
helped: 32
HURT: 18
Fscib are helped.

total bytes in shared programs: 21476424 -> 21475184 (<.01%)
bytes in affected programs: 649884 -> 648644 (-0.19%)
helped: 33
HURT: 18
Bytes are helped.

total regs in shared programs: 865114 -> 865090 (<.01%)
regs in affected programs: 525 -> 501 (-4.57%)
helped: 3
HURT: 0

total uniforms in shared programs: 2120792 -> 2120848 (<.01%)
uniforms in affected programs: 414 -> 470 (13.53%)
helped: 0
HURT: 8
Uniforms are HURT.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
c9e42073a1 agx: optimize signext imad 
improves clpeak short.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Asahi Lina
cf0261980a hk: Enable missing swapchainMaintenance1 support 
This was inconsistent with claiming the extension is supported, and that
trips up GTK4.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
d449800e46 hk: don't advertise impossible modifiers 
fixes dEQP-VK.drm_format_modifiers.bound_to_dma_buf.a2b10g10r10_sint_pack32,Crash

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Asahi Lina
e5d61631fe hk: Fix DRM modifier selection for compressed surfaces 
We have to reject DRM_FORMAT_MOD_APPLE_TWIDDLED_COMPRESSED for surfaces
which are too small. Since the modifier is for all planes, that means
that for multiplane images we need to test all planes for compression
support.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Asahi Lina
da1601a4ec hk: Add virtio implicit sync support 
Since we can't know what BOs are written easily, just sync against all
external BOs.

This should go away once we have proper fence passing support so we can
do implicit sync passing in muvm-x11bridge.

Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Mary Guillemard
1a621a6967 agx: Add support for EGL_NV_context_priority_realtime 
Signed-off-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
ddc6d9e984 agx: fix atomics in tess count shaders 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
2c7635ab63 agx: add tests for sign/zero-extend propagate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:02 +00:00
Alyssa Rosenzweig
6d56c8bc02 agx: fold zext into int sources 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32081>
 2024-11-11 14:33:01 +00:00