Remove the temporary ntr_src/ntr_dst representation by translating NIR
sources and destinations straight to backend rc_src_register and
rc_dst_register values.
Keep the NIR translator instruction state in backend rc_sub_instruction
form as well, so this path no longer has to stage ureg-shaped registers
before emitting backend instructions.
The only slightly ugly part is saturate, since in the backend its not a
dst parameter, but it rather belongs to the instruction.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
ureg_DECL_address just allocates the next sequential TGSI_FILE_ADDRESS
index and returns a ureg_dst. Also backend's dataflow analysis only
ever marks RC_FILE_ADDRESS[0].x as used (see radeon_dataflow.c and
radeon_optimize.c), so any extra address registers were ignored anyway.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Stop using tgsi_get_gl_frag_result_semantic for fragment outputs. The
direct RC path only needs stable output register indices plus the
OutputColor/OutputDepth mappings, so use NIR gl_frag_result locations
instead.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Store rc_opcode directly in struct ntr_insn, populate it with
RC_OPCODE_* values throughout (the few mismatched names get
explicit ntr_OP wrappers: KILL -> KILP, KILL_IF -> KIL), and use
rc_get_opcode_info instead of tgsi_get_opcode_info when walking
the list to emit RC instructions.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Instead of going through the ureg / TGSI tokens / r300_tgsi_to_rc
parsing round-trip, walk the ntr_insn list and rc_constants_add /
rc_insert_new_instruction the result straight into the
radeon_compiler that the caller passes in. Translation reuses the
rc_translate_* helpers extracted in the previous commit.
Changes touching the surrounding code:
- nir_to_rc returns void and takes a struct radeon_compiler *.
- ntr_compile tracks immediates and UBO size in its own
util_dynarray instead of relying on ureg_DECL_immediate /
ureg_DECL_constant2D's bookkeeping.
- ntr_output_decl tracks the FS output color/depth indices so
nir_to_rc can populate compiler->OutputColor[] /
compiler->OutputDepth at the end - find_output_registers is gone.
- r300_translate_{fragment,vertex}_shader drop the tgsi_scan_shader
+ r300_tgsi_to_rc + ttr.error dance and switch to checking
compiler.Base.Error.
- write_all (gl_FragColor vs gl_FragData[0]) now comes from a NIR
walk in r300_translate_fragment_shader rather than reading the
TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS property.
- r300_tgsi_to_rc.{c,h} are deleted, meson.build updated, and the
obsolete header includes go away in r300_fs.c / r300_vs.c.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Pull translate_opcode, translate_register_file, translate_saturate
and the texture-target switch out of r300_tgsi_to_rc into
nir_to_rc.h as static inline rc_translate_* helpers. r300_tgsi_to_rc
now uses them and this is preparation for direct RC emission from
nir_to_rc.c
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
This was moved from r300_optimize_nir previously because we that was
called in finalize_nir and thus could be called more than once. This is
not the case anymore. Also drop the stale nine optimization.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Stop relying on ureg_DECL_immediate's "expand" path to fill earlier
TGSI immediates' unused components with values from later load_const
instructions and depend on later backed pass to do it.
Mostly a wash on shader-db: sub-0.1% regressions on inst/cycles/
consts on RV530/RV370/RV410, with one LOST shader on RV370
(trine/fp-17.shader_test FS).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
Drop the TGSI ureg roundtrip in r300_dummy_fragment_shader and
construct the (0, 0, 0, 1) FS straight via nir_builder, matching
the rest of the compile pipeline that already runs on NIR.
Assisted-by: Codex (GPT-5.5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
