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r300: drop more dead ntr code
This includes some remnants from the regaloc, stale ntr_compile fields, stale comments, unused helpers and one virgl if workaround. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41577>
This commit is contained in:
Pavel Ondračka
Marge Bot
parent
bc89b448c9
commit
d3f9543f2a
1 changed files with 7 additions and 102 deletions
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@ -10,7 +10,6 @@
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#include "compiler/nir/nir_builder.h"
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#include "compiler/nir/nir_deref.h"
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#include "compiler/nir/nir_legacy.h"
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#include "compiler/nir/nir_worklist.h"
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#include "compiler/radeon_code.h"
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#include "compiler/radeon_compiler.h"
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#include "compiler/radeon_program.h"
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@ -29,13 +28,8 @@ struct ntr_immediate {
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float values[4];
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};
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struct ntr_reg_interval {
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uint32_t start, end;
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};
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struct ntr_compile {
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nir_shader *s;
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nir_function_impl *impl;
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struct r300_shader_semantics *semantics;
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/* Options */
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@ -52,18 +46,10 @@ struct ntr_compile {
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struct rc_dst_register *reg_temp;
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struct rc_src_register *ssa_temp;
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struct ntr_reg_interval *liveness;
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unsigned current_if_else;
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unsigned cf_label;
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unsigned num_temps;
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/* Map from NIR driver_location to RC input register. */
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struct rc_src_register *input_index_map;
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uint64_t centroid_inputs;
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uint32_t first_ubo;
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/* RC-side state for direct emission. */
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struct radeon_compiler *compiler;
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@ -357,26 +343,6 @@ ntr_src_as_uint(struct ntr_compile *c, nir_src src)
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return val;
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}
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/* Per-channel masks of def/use within the block, and the per-channel
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* livein/liveout for the block as a whole.
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*/
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struct ntr_live_reg_block_state {
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uint8_t *def, *use, *livein, *liveout, *defin, *defout;
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};
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struct ntr_live_reg_state {
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unsigned bitset_words;
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struct ntr_reg_interval *regs;
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/* Used in propagate_across_edge() */
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BITSET_WORD *tmp_live;
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struct ntr_live_reg_block_state *blocks;
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nir_block_worklist worklist;
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};
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static void
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ntr_read_input_output(struct ntr_compile *c, gl_varying_slot location, unsigned base)
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{
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@ -748,9 +714,8 @@ ntr_get_src(struct ntr_compile *c, nir_src src)
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static struct rc_src_register
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ntr_get_alu_src(struct ntr_compile *c, nir_alu_instr *instr, int i)
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{
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/* We only support 32-bit float modifiers. The only other modifier type
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* officially supported by TGSI is 32-bit integer negates, but even those are
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* broken on virglrenderer, so skip lowering all integer and f64 float mods.
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/* The RC source modifier fields we use here are 32-bit float modifiers.
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* Keep integer and f64 modifiers explicit in NIR.
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*
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* The lower_fabs requests that we not have native source modifiers
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* for fabs, and instead emit MAX(a,-a) for nir_op_fabs.
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@ -1019,10 +984,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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ntr_emit_alu_op2(c, RC_OPCODE_ADD, dst, src[0], ntr_negate(src[1]));
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break;
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case nir_op_fmod:
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UNREACHABLE("should be handled by .lower_fmod = true");
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break;
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case nir_op_fpow:
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ntr_emit_scalar(c, RC_OPCODE_POW, dst, src[0], &src[1]);
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break;
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@ -1043,11 +1004,6 @@ ntr_emit_alu(struct ntr_compile *c, nir_alu_instr *instr)
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ntr_emit_alu_op3(c, RC_OPCODE_CMP, dst, src[0], src[2], src[1]);
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break;
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case nir_op_vec4:
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case nir_op_vec3:
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case nir_op_vec2:
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UNREACHABLE("covered by nir_lower_vec_to_movs()");
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default:
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fprintf(stderr, "Unknown NIR opcode: %s\n", nir_op_infos[instr->op].name);
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UNREACHABLE("Unknown NIR opcode");
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@ -1465,16 +1421,10 @@ ntr_emit_block(struct ntr_compile *c, nir_block *block)
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ntr_emit_instr(c, instr);
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}
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/* Set up the if condition for ntr_emit_if(), which we have to do before
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* freeing up the temps (the "if" is treated as inside the block for liveness
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* purposes, despite not being an instruction)
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*
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* Note that, while IF and UIF are supposed to look at only .x, virglrenderer
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* looks at all of .xyzw. No harm in working around the bug.
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*/
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/* Set up the if condition for ntr_emit_if(). */
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nir_if *nif = nir_block_get_following_if(block);
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if (nif)
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c->if_cond = ntr_scalar(ntr_get_src(c, nif->condition), RC_SWIZZLE_X);
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c->if_cond = ntr_get_src(c, nif->condition);
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}
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static void
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@ -1529,8 +1479,6 @@ ntr_add_constants(struct ntr_compile *c)
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static void
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ntr_emit_impl(struct ntr_compile *c, nir_function_impl *impl)
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{
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c->impl = impl;
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c->ssa_temp = rzalloc_array(c, struct rc_src_register, impl->ssa_alloc);
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c->reg_temp = rzalloc_array(c, struct rc_dst_register, impl->ssa_alloc);
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@ -1547,8 +1495,6 @@ ntr_emit_impl(struct ntr_compile *c, nir_function_impl *impl)
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/* Add constants referenced by the emitted RC instructions. */
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ntr_add_constants(c);
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ralloc_free(c->liveness);
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c->liveness = NULL;
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}
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static int
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@ -1568,42 +1514,6 @@ ntr_should_vectorize_instr(const nir_instr *instr, const void *data)
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return 4;
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}
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static bool
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ntr_should_vectorize_io(unsigned align, unsigned bit_size, unsigned num_components,
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unsigned high_offset, nir_intrinsic_instr *low, nir_intrinsic_instr *high,
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void *data)
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{
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if (bit_size != 32)
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return false;
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/* Our offset alignment should always be at least 4 bytes */
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if (align < 4)
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return false;
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/* No wrapping off the end of a TGSI reg. We could do a bit better by
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* looking at low's actual offset. XXX: With LOAD_CONSTBUF maybe we don't
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* need this restriction.
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*/
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unsigned worst_start_component = align == 4 ? 3 : align / 4;
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if (worst_start_component + num_components > 4)
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return false;
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return true;
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}
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static nir_variable_mode
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ntr_no_indirects_mask(nir_shader *s, struct pipe_screen *screen)
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{
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unsigned pipe_stage = s->info.stage;
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unsigned indirect_mask = nir_var_shader_in | nir_var_shader_out;
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if (!screen->shader_caps[pipe_stage].indirect_temp_addr) {
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indirect_mask |= nir_var_function_temp;
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}
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return indirect_mask;
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}
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struct ntr_lower_tex_state {
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nir_scalar channels[8];
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unsigned i;
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@ -1788,14 +1698,9 @@ nir_to_rc(struct nir_shader *s, struct pipe_screen *screen,
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ntr_fixup_varying_slots(s, s->info.stage == MESA_SHADER_FRAGMENT ? nir_var_shader_in : nir_var_shader_out);
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/* Lower array indexing on FS inputs. Since we don't set
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* ureg->supports_any_inout_decl_range, the TGSI input decls will be split to
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* elements by ureg, and so dynamically indexing them would be invalid.
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* Ideally we would set that ureg flag based on
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* pipe_shader_caps.tgsi_any_inout_decl_range, but can't due to mesa/st
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* splitting NIR VS outputs to elements even if the FS doesn't get the
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* corresponding splitting, and virgl depends on TGSI across link boundaries
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* having matching declarations.
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/* The fragment backend doesn't support relative addressing of input
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* sources, so lower array indexing on FS inputs before nir_lower_io turns
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* derefs into load_input offsets.
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*/
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if (s->info.stage == MESA_SHADER_FRAGMENT) {
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NIR_PASS(_, s, nir_lower_indirect_derefs_to_if_else_trees,
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