Commit graph

82416 commits

Author SHA1 Message Date
Brian Paul
96909ef128 spirv: add switch case for nir_texop_txf_ms_mcs in vtn_handle_texture()
Mark it as unreachable.  Silences a compiler warning:

spirv/spirv_to_nir.c:1397:4: warning: enumeration value
'nir_texop_txf_ms_mcs' not handled in switch [-Wswitch]
    switch (instr->op) {
    ^

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2016-05-18 14:57:45 -06:00
Matt Turner
9c290b1e54 Revert "i965/urb: fixes division by zero"
This reverts commit 2a8aa1e3de.
2016-05-18 12:48:50 -07:00
Ardinartsev Nikita
2a8aa1e3de i965/urb: fixes division by zero
Fixes regression introduced by af5ca43f26

Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
2016-05-18 11:09:37 -07:00
Matt Turner
caab3cd536 mesa: fclose() filename on error.
Pretty useless, as it's in debugging code. Found by Coverity (CID
1257016).
2016-05-18 11:09:37 -07:00
Matt Turner
cbb0e3a7e8 i965/fs: Assert that nir_op_extract_*'s src1 is a constant. 2016-05-18 11:09:37 -07:00
Matt Turner
6a4ff51f7a glsl: Check that layout is non-null before dereferencing.
layout should only be null for structs, but it's checked everywhere else
and confuses Coverity (CID 1358495).

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 11:09:37 -07:00
Matt Turner
53f64a8404 egl/dri2: Don't check return result of mtx_unlock().
Coverity (CID 1358496) warns that the cleanup code doesn't unlock the
mutex (which is arguably kind of stupid, since the only case that can
happen is when mtx_unlock() failed!). But, mtx_unlock() isn't going to
fail -- the mutex was locked by this thread just a few lines above it.
2016-05-18 11:09:37 -07:00
Matt Turner
b1e6d069da spirv: Properly size the src[] array.
Operations like nir_op_bitfield_insert have four arguments, and Coverity
isn't privy to the fact that 4-argument operations aren't possible here,
so it thinks this can lead to memory corruption. Just increase the size
of the array to quell any fears.
2016-05-18 11:09:37 -07:00
Matt Turner
0a548eb56f isl: Mark default cases in switch unreachable.
To silence -Wmaybe-uninitialized warnings.
2016-05-18 11:09:37 -07:00
Ian Romanick
7619aed41d glsl/linker: Ensure the first stage of an SSO pipeline has input locs assigned
Previously an SSO pipeline containing only a tessellation control shader
and a tessellation evaluation shader would not get locations assigned
for the TCS inputs.  This would lead to assertion failures in some
piglit tests, such as arb_program_interface_query-resource-query.

That piglit test still fails on some tessellation related subtests.
Specifically, these subtests fail:

'GL_PROGRAM_INPUT(tcs) active resources' expected 2 but got 3
'GL_PROGRAM_INPUT(tcs) max length name' expected 12 but got 16
'GL_PROGRAM_INPUT(tcs,tes) active resources' expected 2 but got 3
'GL_PROGRAM_INPUT(tcs,tes) max length name' expected 12 but got 16
'GL_PROGRAM_OUTPUT(tcs) active resources' expected 15 but got 3
'GL_PROGRAM_OUTPUT(tcs) max length name' expected 23 but got 12

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
2016-05-18 10:53:50 -07:00
Ian Romanick
79bbff9def glsl/linker: Don't include interface name for built-in blocks
Commit 11096ec introduced a regression in some piglit tests (e.g.,
arb_program_interface_query-resource-query).  I did not notice this
regression because other (unrelated) problems caused failed assertions
in those same tests on my system... so they crashed before getting to
the new failure.

v2: Use is_gl_identifier.  Suggested by Tim.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
2016-05-18 10:53:34 -07:00
Ian Romanick
2ef4b5bc93 glsl: Assert that inputs have a location assigned
This catches a problem previously undetected until deep in the backend.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Ian Romanick
cf9220b11f glsl/linker: Fix trivial typos in comments
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Ian Romanick
d2579728c9 glsl/linker: Fix some formatting to match current coding conventions
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Ian Romanick
02e4753777 glsl/linker: Silence unused parameter warning
The use of the parameter was removed in d6b92028.

glsl/link_varyings.cpp:1390:39: warning: unused parameter ‘separate_shader’ [-Wunused-parameter]
                                   bool separate_shader)
                                       ^

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Ian Romanick
75c9aa6670 glsl/linker: Silence unused parameter warning
The parameter appears to have been unused since the function was added
in commit 12ba6cfb.  Remove it.

glsl/linker.cpp:2886:60: warning: unused parameter ‘prog’ [-Wunused-parameter]
 match_explicit_outputs_to_inputs(struct gl_shader_program *prog,
                                                            ^

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Ian Romanick
f687b8e178 i965: Silence unused parameter warnings
The only place that actually used the type parameter was the GS visitor,
and it was always passed glsl_type::int.  Just remove the parameter.

brw_vec4_vs_visitor.cpp:38:61: warning: unused parameter ‘type’ [-Wunused-parameter]
                                            const glsl_type *type)
                                                             ^

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-05-18 10:53:34 -07:00
Daniel Scharrer
1d628ea09d mesa: Don't advertise GLES 3.1 without compute support
The MaxComputeWorkGroupInvocations constant is used in
compute_version_es2() instead of extensions->ARB_compute_shader
as ES has lower requirements than desktop GL.

Both i965 and gallium set this constant before enabling compute support.

Signed-off-by: Daniel Scharrer <daniel@constexpr.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2016-05-18 18:21:21 +02:00
Rob Clark
5827a1dc4b mesa/st: don't leak name
Pointed out by coverity.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-18 09:20:22 -04:00
Brian Paul
877a8026c7 svga: null out all sampler views if start=num=0
Because the CSO module handles sampler views for fragment shaders
differently than vertex/geom shaders, VS/GS shader sampler views
aren't explicitly unbound like for FS sampler vers.  This code
checks for the case of start=num=0 and nulls out the sampler views.
Fixes a assert regression in piglit's arb_texture_multisample-
sample-position test.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-05-17 19:20:36 -06:00
Brian Paul
fe430b0310 st/mesa: remove unused st_context::default_texture
The code which used this was removed quite a while ago.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2016-05-17 19:20:36 -06:00
Brian Paul
5888c47cc9 cso: remove / add some comments
Signed-off-by: Brian Paul <brianp@vmware.com>
2016-05-17 19:20:36 -06:00
Eric Anholt
18260d0582 vc4: Add support for vertex color clamping in the rasterizer.
This gets us precompile of vertex shaders at the state tracker level as
well.
2016-05-17 18:09:58 -07:00
Eric Anholt
474e2bbcc1 vc4: Move tgsi_to_nir to precompile time.
Now we have an immutable nir shader in our shader's CSO that we can clone
and lower/optimize.
2016-05-17 18:07:39 -07:00
Eric Anholt
734fe41092 vc4: Mark the driver as supporting fragment color clamping in rast.
We always clamp fragment colors, since they're always 8-bit unorm, so
there's no need to have us compile separate shaders based on
GL_ARB_color_buffer_float.  This gives us precompilation of fragment
programs to the vc4_shader_state_create() level.
2016-05-17 18:07:39 -07:00
Eric Anholt
8835eb689b vc4: Enable sharing shaders across contexts.
This allows the same pipe_shader_state to be referenced from multiple
contexts.  Since our pipe_shader_state is treated as immutable (other than
the variant number) within the driver, this is no problem.
2016-05-17 18:07:39 -07:00
Eric Anholt
62087cb9b8 vc4: Switch to using nir_load_front_face.
This will be generated by glsl_to_nir, and it turns out that this is a
more code-efficient path than the floating point math, anyway.

No change on shader-db, but drops an instruction in piglit's
glsl-fs-frontfacing.
2016-05-17 18:07:39 -07:00
Eric Anholt
0700e4c0c7 vc4: Drop the dead export_linkage array.
This came from deriving from freedreno.
2016-05-17 18:07:39 -07:00
Eric Anholt
24e7e3d3fc vc4: Fix a -Wformat-security warning.
This is apparently enabled as an error in Android builds, and the compiler
can't tell that the return value is safe.
2016-05-17 18:07:39 -07:00
Alex Deucher
86f51d7958 radeonsi: add new polaris11 pci ids
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-17 17:49:50 -04:00
Alex Deucher
768320b497 radeonsi: add new polaris10 pci ids
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2016-05-17 17:49:50 -04:00
Kenneth Graunke
dc657a8201 i965: Make brw_reg_from_fs_reg() halve exec_size when compressed.
In a5d7e144ea, Connor generalized the
exec_size halving code to handle more cases.  As part of this, he made
it not halve anything if the region accessed falls completely in a
single register.

Unfortunately, it started producing some invalid regions:

-add(16)  g6<1>F  g10<8,8,1>UW    -g1<0,1,0>F    { align1 compr };
-add(16)  g8<1>F  g12<8,8,1>UW    -g1.1<0,1,0>F  { align1 compr };
+add(16)  g6<1>F  g10<16,16,1>UW  -g1<0,1,0>F    { align1 compr };
+add(16)  g8<1>F  g12<16,16,1>UW  -g1.1<0,1,0>F  { align1 compr };

Here, the UW source region completely fits within a register.  However,
we have to use instruction compression because the destination region
spans two registers.  <16,16,1> is invalid because it's compressed.

To handle this, skip the "everything fits in one register" case and
fall through to the exec_size halving case when compressed.

Fixes hundreds of Piglit regressions on GM965.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-17 14:40:37 -07:00
Kenneth Graunke
062ad81669 i965: Move compression decisions before brw_reg_from_fs_reg().
brw_reg_from_fs_reg() needs to know whether the instruction will be
compressed or not.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95370
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-05-17 14:40:31 -07:00
Kenneth Graunke
9a1936d965 i965: Enable ES 3.2 sample shading extensions.
This enables:
- GL_OES_sample_shading
- GL_OES_sample_variables
- GL_OES_shader_multisample_interpolation

On Gen8, we pass all the CTS tests, and all but 4 of the dEQP-GLES31
tests (dealing with 1x/2x MSAA at half rate sampling).  We believe
those 4 dEQP-GLES31 tests are incorrect.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-05-17 14:27:29 -07:00
Jordan Justen
1ff212bfd3 anv: Fix warning: unused variable ‘cs_prog_data’
This was introduced in 8a80af2820.

Reported-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
2016-05-17 14:09:56 -07:00
Mauro Rossi
0e81336550 android: fix building error in libmesa_st_mesa
Fixes the following building error due to libmesa_nir dependency:

In file included from external/mesa/src/mesa/state_tracker/st_glsl_to_nir.cpp:44:0:
external/mesa/src/compiler/nir/nir.h:42:25: fatal error: nir_opcodes.h: No such file or directory
 #include "nir_opcodes.h"
                         ^
compilation terminated.
build/core/binary.mk:706: recipe for target 'out/target/product/x86/obj/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/state_tracker/st_glsl_to_nir.o' failed
make: *** [out/target/product/x86/obj/STATIC_LIBRARIES/libmesa_st_mesa_intermediates/state_tracker/st_glsl_to_nir.o] Error 1
make: *** Waiting for unfinished jobs....

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-17 17:07:28 -04:00
Nicolai Hähnle
941756f092 radeonsi: force level zero on image instructions in non-fragment shaders (v2)
Section 8.9 (Texture Functions) of the OpenGL Shading Language 4.5
specification:

   However, automatic level of detail is computed only for fragment shaders.
   Other shaders operate as though the base level of detail were computed as
   zero.

and Section 8.9.3 (Texture Gather Functions):

   When performing a texture gather operation, the minification and
   magnification filters are ignored, and the rules for LINEAR filtering in
   the OpenGL Specification are applied to the base level of the texture
   image to identify the four texels i_0 j_1, i_1 j_1, i_1 j_0, and i_0 j_0.

Of course, explicit LOD or derivative variants work in all shader types.

This fixes several GL4x-CTS.texture_gather.* tests.

v2: TG4 is always level zero (thanks, Ilia)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:40 -05:00
Nicolai Hähnle
988fd6c922 radeonsi: emit TXQ in separate functions
TXQ is sufficiently different that having in it in the same code path as
texture sampling/fetching opcodes doesn't make much sense.

v2: guard against NULL pointer dereferences

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
2016-05-17 15:28:40 -05:00
Nicolai Hähnle
d464bfd12a winsys/amdgpu: cleanup error handling in amdgpu_ctx_create
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:40 -05:00
Nicolai Hähnle
fef08af99c winsys/amdgpu: avoid ioctl call when fence_wait is called without timeout
When user fences are used, we don't need the kernel for polling.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:39 -05:00
Nicolai Hähnle
0558564200 gallium/radeon: add radeon_emitted to check for non-trivial IBs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:39 -05:00
Nicolai Hähnle
5e89b027b9 gallium/radeon: use radeon_emit_array
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:39 -05:00
Nicolai Hähnle
c23273532e gallium/radeon: use radeon_emit
Mostly generated using a sed-script, with manual fix-up for multi-line
statements.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:38 -05:00
Nicolai Hähnle
4ac555e9e5 st/mesa: fix reversed copyimage canonical format
The format_desc swizzle describes where in the array each color channel
comes from - but the existing code was written as if each entry in the
swizzle described the meaning of an array element.

Fixes piglit's arb_copy_image-format-swizzle.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:38 -05:00
Jordan Justen
6c9f35bb73 Revert "HACK: Don't re-configure L3$ in render stages pre-BDW"
This reverts commit 41af9b2e51.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94468
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jordan Justen
8a80af2820 anv: Port L3 cache programming from i965
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jordan Justen
aa41de080d anv/gen7: Add memory barrier to vkCmdWaitEvents call
We also have this barrier call for gen8 vkCmdWaitEvents.

We don't implement waiting on events for gen7 yet, but this barrier at
least helps to not regress CTS cases when data caching is enabled.
Without this, the tests would intermittently report a failure when the
data cache was enabled.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jordan Justen
8ee31828c6 anv: Keep track of whether the data cache should be enabled in L3
If images or shader buffers are used, we will enable the data cache in
the the L3 config.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jordan Justen
ff41738871 genxml/hsw: Add L3 cache control registers
These were added to the i965 driver in
5912da45a6.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-05-17 13:04:03 -07:00
Jan Vesely
47b390fe45 Treewide: Remove Elements() macro
Signed-off-by: Jan Vesely <jano.vesely@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-05-17 15:28:04 -04:00