Commit graph

166555 commits

Author SHA1 Message Date
Danylo Piliaiev
43ea1f2dfb freedreno: Document A6XX_GRAS_SC_CNTL::rotation field
Likely used for VK_QCOM_render_pass_transform.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev
388e4ea733 tu: Prevent using stale value of GRAS_SC_CNTL in sysmem clear
cc: mesa-stable

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Danylo Piliaiev
981f1d88a1 tu: Prevent using stale value of RB_UNKNOWN_88D0 on BLIT
Fixes: def56b531c
("tu: Support GMEM with layered rendering and multiview")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21148>
2023-02-10 20:29:40 +00:00
Amber
99fb770c45 freedreno: use blendcoherent to set FLUSH_PER_OVERLAP
FLUSH_PER_OVERLAP is only necessary for gmem if coherent blending is
enabled.

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Amber
527a74cb5d gallium: make BlendCoherent usable from gallium drivers
Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Amber
40bdd2bbf7 freedreno: use A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE with fb readback
fixes:
dEQP-GLES31.functional.blend_equation_advanced.msaa.*

Signed-off-by: Amber Amber <amber@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21161>
2023-02-10 20:01:43 +00:00
Mike Blumenkrantz
cd446b87e1 zink: add newlines to some debug printfs
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21239>
2023-02-10 19:42:53 +00:00
Väinö Mäkelä
13f68bcce1 hasvk: Tell spirv_to_nir float controls are always supported
This gets rid of the "Unsupported SPIR-V capability" warnings when
compiling shaders using float controls on gfx7.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä
6f932276c3 hasvk: Don't claim shaderDenormPreserveFloat32 on gfx7
From the Haswell PRM Vol. 7, "IEEE Floating Point Mode":
     "Single precision (F, Float) denorms are flushed to sign-preserved
      zero on input and output of any floating-point mathematical
      operation."

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä
56667002fd intel/vec4: Don't optimize multiply by 1.0 away
The SPIR-V compiler's implementation of tanh generates a multiply by 1.0
to flush denorms to zero.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:01 +00:00
Väinö Mäkelä
dcad4a2cd1 intel/vec4: Set the rounding mode
The rounding mode only needs to be set once, because 16-bit floats or
preserving denorms aren't supported for the platforms where vec4 is
used.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20232>
2023-02-10 16:34:00 +00:00
Eric Engestrom
5a2326f9b2 panfrost: drop no-longer-needed libglsl
Fixes: 551c2aadd4 ("pan/bi: Remove standalone compiler")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21240>
2023-02-10 14:09:37 +00:00
Samuel Pitoiset
bd30f3619d radv: implement graphics shaders relocation for a RGP workaround
RGP requires shaders to be uploaded consecutively inside the same
buffer object. Otherwise, either it makes the driver generating
huge traces (ie. in GiB) or it fails to load traces at all. Hopefully,
this will be improved soon when AMDGPU drivers will have GPL support.

To workaround this, the driver relocates graphics shaders in the same
buffer object when a pipeline is created. Then at draw time, it
overwrites SPI_SHADER_PGM_xxx registers to make sure SQTT can match
between emitted and exported shaders. It's a bit suboptimal because
graphics shaders are uploaded twice but it's the best solution I found.

This will allow to implement GPL caching without breaking capturing
shaders with RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
2023-02-10 13:42:14 +00:00
Samuel Pitoiset
69bd1c0c40 radv: restore uploading shaders individually instead of consecutively
The shaders were uploaded consecutively to fit a RGP constraint but
this was more like a workaround. This upload path doesn't work well for
graphics pipeline library and it was the main blocker for GPL caching.

This commit breaks capturing shaders with RGP if the offset between
shaders is too big. Next commit should fix it by using shaders reloc.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21078>
2023-02-10 13:42:14 +00:00
Georg Lehmann
533d0008c7 aco: remove stale TODOs about v_interp opsel
These are already handled correctly according to the ISA docs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21096>
2023-02-10 12:01:56 +00:00
Philipp Zabel
f29f656530 vulkan/wsi/wayland: fix acquire_next_image to report timeouts properly
The Vulkan Specification states about possible return values from
vkAcquireNextImageKHR:

 * VK_NOT_READY is returned if timeout is zero and no image was
   available.
 * VK_TIMEOUT is returned if timeout is greater than zero and less than
   UINT64_MAX, and no image beae available within the time allowed.

That is, if info->timeout is larger than zero, the function must return
VK_TIMEOUT instead of VK_NOT_READY if no image became available before
the timeout elapsed.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21190>
2023-02-10 11:32:54 +00:00
Samuel Pitoiset
75ccf7c003 radv/ci: bump the number of runners to 3 for vkcts-navi21-valve
RADV_PERFTEST=gpl increased execution time, so let's try with a 3d
runner.

dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
seems reliably fixed now for some reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
2023-02-10 11:06:54 +01:00
Samuel Pitoiset
6533709d10 radv/ci: set RADV_PERFTEST=GPL for all VKCTS jobs
The Vulkan CTS version in Mesa CI is so old that a bunch of tests
are broken, but it's expected.

This runs +283939 tests and the overall VKCTS execution time increased
from ~23 minutes to ~26 minutes (+~13%) on my Threadripper 1950X.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21214>
2023-02-10 11:06:54 +01:00
Pavel Ondračka
94eff7ccd8 nir: shrink phi nodes in nir_opt_shrink_vectors
While this change helps with few shaders, the main benefit is
that it allows to unroll loops comming from nine+ttn on vec4
backends. D3D9 REP ... ENDREP type loops are unrolled now already,
LOOP ... ENDLOOP need some nine changes that will come later.

r300 RV530 shader-db:
total instructions in shared programs: 132481 -> 132344 (-0.10%)
instructions in affected programs: 3532 -> 3395 (-3.88%)
helped: 13
HURT: 0

total temps in shared programs: 16961 -> 16957 (-0.02%)
temps in affected programs: 88 -> 84 (-4.55%)
helped: 4
HURT: 0

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8102
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7222

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21038>
2023-02-10 09:06:25 +00:00
Samuel Pitoiset
2a008018c1 docs: stop reporting RADV_PERFTEST=gpl as experimental/suboptimal
The graphics pipeline library implementation in RADV has been
improved considerably lately.

There is still a bit of work for caching individual libraries
and optimized (LTO) pipelines but I think overall it seems good
enough to stop reporting it as experimental and suboptimal.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21213>
2023-02-10 07:59:12 +00:00
Yonggang Luo
09061e2fe9 vulkan: Use static_assert for check HWVULKAN_DISPATCH_MAGIC == ICD_LOADER_MAGIC
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21210>
2023-02-10 07:21:31 +00:00
Chia-I Wu
af7bcc0cdc freedreno: avoid conditional ib in fd6_emit_tile
CP_REG_TEST (or any command that reads registers) is slow on a618
(gen1).  Since SQE can early return, we don't necessarily need
emit_conditional_ib in fd6_emit_tile.

We still CP_REG_TEST twice for load and store when there is no clear.
Not sure if we can simply drop emit_conditional_ib instead?

glmark2 score goes from 943 to 1067.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21208>
2023-02-10 06:31:47 +00:00
Patrick Lerda
b2c340c106 mesa/st: fix possible crash related to arb invalid memory access
This invalid memory access is a consequence of wrong assumptions,
for instance:
"prog->sh.data is NULL if it's ARB_fragment_program"

This issue is triggered with piglit/fp-formats -auto -fbo:
==9747==ERROR: AddressSanitizer: heap-use-after-free on address 0x007f7c812d90 at pc 0x007f833c09f8 bp 0x007fd7eca750 sp 0x007fd7eca768
READ of size 4 at 0x007f7c812d90 thread T0
    #0 0x7f833c09f4 in st_get_sampler_views ../src/mesa/state_tracker/st_atom_texture.c:109
    #1 0x7f833c0b48 in update_textures ../src/mesa/state_tracker/st_atom_texture.c:266
    #2 0x7f82b2d120 in st_validate_state ../src/mesa/state_tracker/st_util.h:128
    #3 0x7f82b2d120 in prepare_draw ../src/mesa/state_tracker/st_draw.c:88
    #4 0x7f82b2de64 in st_draw_gallium ../src/mesa/state_tracker/st_draw.c:141
    #5 0x7f83105940 in _mesa_draw_arrays ../src/mesa/main/draw.c:1202
    #6 0x7f8d5fa5cc in piglit_draw_rect_from_arrays piglit/tests/util/piglit-util-gl.c:711
    #7 0x7f8d5fac34 in piglit_draw_rect_custom piglit/tests/util/piglit-util-gl.c:833
    #8 0x4019e0 in piglit_display piglit/tests/shaders/fp-formats.c:67
    #9 0x7f8d643fc4 in run_test piglit/tests/util/piglit-framework-gl/piglit_fbo_framework.c:52
    #10 0x401624 in main piglit/tests/shaders/fp-formats.c:39

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21175>
2023-02-10 04:45:29 +00:00
Chia-I Wu
620baf9c42 freedreno/registers: document more bits of CP_REG_TEST
On gen3+, there are 32 predicate bits instead of 1.

I set out to see why CP_REG_TEST (and others commands that read
registers) is slower on gen1 but could not find anything.  Since the
blob seems to use multiple predicate bits, let's keep them documented.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
2023-02-10 04:12:08 +00:00
Chia-I Wu
0278462575 turnip: skip unnecessary CP_REG_TEST for cond load/store
When no attachment allows conditional load/store, skip the unnecessary
CP_REG_TEST.

This is done to avoid a performance trap on a618 (gen1).  CP_REG_TEST or
any command that reads a register is slow on a618.

glmark2 score goes from 830 to 1001.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8162
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
2023-02-10 04:12:08 +00:00
Chia-I Wu
37f6714fe7 turnip: add a comment to tu_render_pass_cond_config
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21206>
2023-02-10 04:12:08 +00:00
Mike Blumenkrantz
487ac6dbd6 zink: implement cross-program pipeline library sharing
some games/apps (e.g., DOOM2016) compile+link shaders in one context
and then use them in another, expecting that the compiled shaders
will be reused. vulkan has pipeline (library) objects, which are not
specific to shaders but are in theory representing the shaders being used

thus, pipeline (library) objects need to be reusable for any case where
a shader can be reused

to handle this:
* extract pipeline library cache to a refcounted object
* store these objects on the screen
* make them owned by shaders

separable programs are slightly different since they'll use their own
fastpath, thus making their library caches owned by the programs to avoid
polluting the optimized caches

fixes #8264

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
2023-02-10 03:53:46 +00:00
Mike Blumenkrantz
b282761839 zink: break out zink_gfx_program::libs into refcounted object
no functional changes yet, and these are still 1:1 with their programs

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
2023-02-10 03:53:46 +00:00
Mike Blumenkrantz
6482cf12ca zink: store gfx_hash on zink_gfx_program
this avoids needing to reference ctx->gfx_hash in threads or recalc the hash

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21223>
2023-02-10 03:53:46 +00:00
Ian Romanick
18fc4daaf6 nir/inline_uniforms: Add inot condition support
From the 96c19d23c9 commit message:

    Ever since 4246c2869c and 7d85dc4f35 loop unrolling can no
    longer depend on inot being eliminated from the loop
    terminator condition so we need to be able to handle it.

Support these conditions here too.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
682e83f012 nir/inline_uniforms: Make add_inlinable_uniforms public
This is step 5 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
cdd23b1efa nir/inline_uniforms: Make src_only_uses_uniforms public, change name
While making the function public, rename it to
nir_collect_src_uniforms. The old name makes it sound like it's just a
query that doesn't have side effects. That is, however, not the case.

This is step 4 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
edb89b71c5 nir/inline_uniforms: Allow possibility of uni_offsets and num_offsets being NULL
This is step 3 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
0c0fb216dd nir/inline_uniforms: Allow possibility of more than one UBO
Only caller in this file still only passes 1.

This is step 2 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
23b4266f9e nir/inline_uniforms: Pass max_num_bo and max_offset around as parameters
max_num_bo is currently limited to 1. That will change in the next
commit.

This is step 1 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Ian Romanick
1d5033823e nir/inline_uniforms: Change num_offsets type to uint8_t
This is step 0 in an attempt to unify a bunch of nir_inline_uniforms.c
and lvp_inline_uniforms.c code.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21179>
2023-02-10 03:18:23 +00:00
Emma Anholt
6b6f757e23 ci/crocus: Update HSW expectations.
2 good-looking trace updates, one new crash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
b01c3553f7 ci/radv: Update navi21 llvm xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
9adfe49563 ci/nouveau: Disable the gm20b jobs entirely.
The old (broken, hw failure) board isn't really hooked up right now, and
I'm waiting on buying some remaining bits to set up the 10 boards sitting
in the box here.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
ba73aaa0da ci/freedreno: Update a3xx piglit_shader xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
e182970692 ci/freedreno: Add an xfail for a618 VK full run.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
a8a6be1641 ci/freedreno: Update a530 manual-run xfails.
A lot of this looks like fractional run test list updates.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
e267d72979 ci/freedreno: Disable the a306_piglit_gl job.
It's broken with recurring hangchecks.  Someone would need to restabilize
it, but turn it off for anyone to find until someone (me? :( ) cares.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
238fcd30ed ci/zink: Update TGL full-run xfails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Emma Anholt
1a862c74bc ci: Disable systems in my farm that haven't recovered.
We lost power in a storm, and these ones didn't come back afterwards.  I
suspect I need a new PSU.  And maybe some surge protection for the future.
:(

I've left the CI code in place for some day when I hopefully swap out the
power supplies.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21205>
2023-02-10 02:53:09 +00:00
Nanley Chery
2e13456bca mesa/st: Measure compressed fallback unmap paths
Add code to help find performance issues. The logging is disabled by
default.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
2023-02-10 01:40:47 +00:00
Nanley Chery
fdabf886be mesa/st: Enable compute-based transcoding to DXT5
By enabling this path, we get a 56% decrease in upload time on a texture
upload microbenchmark. This was measured on an Ice Lake with an iris
driver that tries to use the compressed format fallback path.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
2023-02-10 01:40:47 +00:00
Nanley Chery
6d57614fd0 mesa/st: Add st_texture_image_resource_level
Returns the level of the gl_texture_image with respect to the resource
it's allocated within. Example: returns 0 for non-finalized texture.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
2023-02-10 01:40:47 +00:00
Nanley Chery
637ff22413 mesa/st: Add st_compute_transcode_astc_to_dxt5
Add a function to upload ASTC data, transcoding it to BC3/DXT5 in the
process.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
2023-02-10 01:40:47 +00:00
Nanley Chery
1f8f1a0d9b mesa/st: Add and use create_bc1_endpoint_ssbo
Create and cache the SSBO used by the BC1 compute shader program.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19827>
2023-02-10 01:40:47 +00:00