fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 04:48:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

aco: remove stale TODOs about v_interp opsel

Browse source 
These are already handled correctly according to the ISA docs.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21096>
This commit is contained in:
Georg Lehmann 2023-02-03 14:46:29 +01:00 • committed by Marge Bot
parent f29f656530
commit 533d0008c7
1 changed files with 0 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/amd/compiler/aco_ir.cpp
View file

@ -463,7 +463,6 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx)
case aco_opcode::v_mad_i32_i16: return idx >= 0 && idx < 2;
case aco_opcode::v_dot2_f16_f16:
case aco_opcode::v_dot2_bf16_bf16: return idx == -1 || idx == 2;
// TODO: This matches what LLVM allows. We should see if this matches what the hardware allows.
case aco_opcode::v_interp_p10_f16_f32_inreg:
case aco_opcode::v_interp_p10_rtz_f16_f32_inreg: return idx == 0 || idx == 2;
case aco_opcode::v_interp_p2_f16_f32_inreg:
@ -475,8 +474,6 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx)
bool
instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op)
{
// TODO: VINTERP (v_interp_p2_f16_f32, v_interp_p2_rtz_f16_f32)
/* partial register writes are GFX9+, only */
if (gfx_level < GFX9)
return false;