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freedreno: avoid conditional ib in fd6_emit_tile

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CP_REG_TEST (or any command that reads registers) is slow on a618
(gen1).  Since SQE can early return, we don't necessarily need
emit_conditional_ib in fd6_emit_tile.

We still CP_REG_TEST twice for load and store when there is no clear.
Not sure if we can simply drop emit_conditional_ib instead?

glmark2 score goes from 943 to 1067.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21208>
This commit is contained in:
Chia-I Wu 2023-02-08 15:14:55 -08:00 • committed by Marge Bot
parent b2c340c106
commit af7bcc0cdc
1 changed files with 1 additions and 5 deletions
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6
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
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@ -1439,11 +1439,7 @@ prepare_tile_fini_ib(struct fd_batch *batch) assert_dt
static void
fd6_emit_tile(struct fd_batch *batch, const struct fd_tile *tile)
{
if (!use_hw_binning(batch)) {
fd6_emit_ib(batch->gmem, batch->draw);
} else {
emit_conditional_ib(batch, tile, batch->draw);
}
fd6_emit_ib(batch->gmem, batch->draw);
if (batch->tile_epilogue)
fd6_emit_ib(batch->gmem, batch->tile_epilogue);