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Author SHA1 Message Date
Timur Kristóf
58e3b1f930 aco: Allow passing constant operand to is_overwritten_since. 
This is to make it more intuitive and also consistent
with last_writer_idx which does allow constant operands.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28046>
 2024-03-19 20:50:12 +00:00
Konstantin Seurer
a6b93c50d0 radv/printf: Use fprintf instead of printf 
For using other destinations than stdout.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28228>
 2024-03-19 19:05:25 +00:00
Konstantin Seurer
d902b6d805 radv: Skip more acceleration structure build markers 
We should skip even more stuff when using updates only.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28228>
 2024-03-19 19:05:25 +00:00
Konstantin Seurer
6095b70f85 radv/rt: Use 32-bit offsets for load_sbt_entry 
Totals from 82 (18.06% of 454) affected shaders:
MaxWaves: 820 -> 821 (+0.12%)
Instrs: 2765694 -> 2766338 (+0.02%); split: -0.08%, +0.10%
CodeSize: 14751988 -> 14735464 (-0.11%); split: -0.13%, +0.01%
VGPRs: 8464 -> 8448 (-0.19%)
SpillSGPRs: 454 -> 512 (+12.78%)
Latency: 19368679 -> 19344967 (-0.12%); split: -0.21%, +0.09%
InvThroughput: 5354427 -> 5346317 (-0.15%); split: -0.24%, +0.08%
VClause: 100183 -> 100331 (+0.15%); split: -0.02%, +0.17%
SClause: 66584 -> 66590 (+0.01%); split: -0.02%, +0.03%
Copies: 237008 -> 238684 (+0.71%); split: -0.53%, +1.23%
Branches: 113344 -> 113386 (+0.04%); split: -0.00%, +0.04%
PreSGPRs: 6141 -> 6194 (+0.86%)
PreVGPRs: 7916 -> 7880 (-0.45%)

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27725>
 2024-03-19 17:03:28 +00:00
Konstantin Seurer
00dec03438 radv: Use radv_buffer_map for parsing IBs 
We need matching pointers pointers for annotations to work.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:14 +00:00
Konstantin Seurer
a78cbc98cc ac: Improve context roll readability 
Add new lines to improve visual separation and color registers:
- red = unchanged
- green = changed

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:14 +00:00
Konstantin Seurer
1d747653d4 radv: Add an IB annotation layer 
The layer annotates the command buffers with api
entrypoint names.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:14 +00:00
Konstantin Seurer
8f0ee3a92b radv: Add support for IB annotations 
Wires up ac_parse_ib annotation support.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:14 +00:00
Konstantin Seurer
bf15688fa1 ac/parse_ib: Implement annotations 
Annotates the IB dump with driver specified strings.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:13 +00:00
Konstantin Seurer
0f436e0fe1 ac/parse_ib: Replace the parameter list with ac_ib_parser 
It's more code but it should be more readable. This also makes adding
optional arguments easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:13 +00:00
Konstantin Seurer
2e4d365104 ac: Annotate context rolls 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27549>
 2024-03-19 16:08:13 +00:00
Timur Kristóf
8f3cc3cb29 radv: Use mapped driver locations for determining I/O strides. 
This will allow us to more accurately determine the
input and output strides, because the I/O locations mapped
by RADV don't match the locations in NIR.
As a result, ESO will use less LDS.

It also fixes the per-patch output stride of tess control
shaders, because previously we omitted tess factors from them.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
 2024-03-19 15:01:19 +00:00
Timur Kristóf
2f1f55cf32 radv: Extract input and output stride info to new functions. 
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28021>
 2024-03-19 15:01:19 +00:00
Daniel Schürmann
9bbb9f1104 aco: use small_vec as Block::edge_vec for predecessors and successors 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27984>
 2024-03-19 13:06:58 +00:00
Daniel Schürmann
3e58a736e4 aco/util: small_vec few additions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27984>
 2024-03-19 13:06:58 +00:00
Rhys Perry
5cbd7689be aco/util: add small_vec 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27984>
 2024-03-19 13:06:58 +00:00
Daniel Schürmann
4564ca313b aco: reorder code and use namespaces in aco_interface.cpp 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27984>
 2024-03-19 13:06:58 +00:00
Samuel Pitoiset
4d4b1820ca radv: add radv_force_pstate_peak_gfx11_dgpu and enable it for Helldivers 2 
This seems to definitely improve stability issues (random GPU hangs)
with Helldivers 2 on RDNA3 dGPUs. RDNA3 APUs and other generations
shouldn't be affected.

This is a workaround.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10584
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28260>
 2024-03-19 09:06:43 +00:00
Samuel Pitoiset
9b089ca943 radv: fix occlusion queries with MSAA and no attachments 
The number of samples should be the rasterization samples and not the
framebuffer samples.

Fixes recent dEQP-VK.query_pool.occlusion_query.no_attachments_*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28198>
 2024-03-19 07:19:07 +00:00
Eric Engestrom
ad580a711b radeonsi/ci: udpate expected failures 
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56378175
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56393368
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56414989

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28246>
 2024-03-18 14:03:46 +00:00
Georg Lehmann
67997fd735 aco: avoid full 32bit imul for uniform reduce/scan 
Foz-DB Navi31:
Totals from 24 (0.03% of 79395) affected shaders:
Instrs: 1172275 -> 1172078 (-0.02%)
CodeSize: 5974424 -> 5973860 (-0.01%)
Latency: 5896216 -> 5895923 (-0.00%)
InvThroughput: 1167928 -> 1167869 (-0.01%)
VALU: 625756 -> 625636 (-0.02%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28223>
 2024-03-18 13:37:28 +00:00
Georg Lehmann
96ff511b75 aco/optimizer: combine v_mul_i32_i24 and add to mad 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28223>
 2024-03-18 13:37:28 +00:00
Georg Lehmann
0c57340c23 aco/builder: use 24bit mul if low bits of imm are zero 
Foz-DB Navi31:
Totals from 39 (0.05% of 79395) affected shaders:
Instrs: 62712 -> 62696 (-0.03%)
CodeSize: 330096 -> 329896 (-0.06%)
Latency: 192747 -> 192561 (-0.10%)
InvThroughput: 34078 -> 33889 (-0.55%)
VALU: 38979 -> 38963 (-0.04%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28223>
 2024-03-18 13:37:28 +00:00
Georg Lehmann
b48a101d8f aco/builder: improve v_mul_imm for negative imm 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28223>
 2024-03-18 13:37:27 +00:00
David Rosca
4b7b185711 radv/video: Set maxActiveReferencePictures to 16 for H264/5 
H265 supports 16 reference frames too.

Fixes validation errors when decoding H265 stream with more than 8 reference
frames.

Cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27541>
 2024-03-18 10:04:52 +00:00
Marek Olšák
ba6dfb6ca4 amd/ci: update stoney results 
The dEQP failures are expected.
The occlusion query ones are new flakes, but I don't know what introduced them.
The checksum changes are expected due to new optimizations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26819>
 2024-03-15 19:55:46 +00:00
Samuel Pitoiset
67fd490fe5 radv: add a GPU hang workaround for legacy tess+GS for GFX10.3 
Ported from RadeonSI ea94cb95e4
("radeonsi/gfx10.3: add a GPU hang workaround for legacy tess+GS")

Fixes: a23802bcb9 ("ac,radeonsi: start adding support for gfx10.3")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
 2024-03-15 16:38:14 +00:00
Samuel Pitoiset
96e9c3fe77 radv: program SAMPLE_MASK_TRACKER_WATERMARK optimally for GFX11 APUs 
Ported from RadeonSI 6ce3a95852
("radeonsi/gfx11: program SAMPLE_MASK_TRACKER_WATERMARK optimally for APUs")

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
 2024-03-15 16:38:14 +00:00
Samuel Pitoiset
d81809618f radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11 
Ported from RadeonSI 7d3a414662
("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT")

Fixes: 25a66477d0 ("radeonsi/gfx11: register changes")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
 2024-03-15 16:38:14 +00:00
Samuel Pitoiset
8203284c03 radv: disable binning correctly on GFX11.5 
Ported from RadeonSI 20445f296b
("radeonsi: disable binning correctly on gfx11.5").

Fixes: b44a886b84 ("amd/common: add registers for gfx11.5")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28165>
 2024-03-15 16:38:14 +00:00
Samuel Pitoiset
6146a1651a radv: emit VGT_GS_OUT_PRIM_TYPE as part of the dynamic primitive topology 
With pipelines, the topology class is known at creation time but with
ESO this needs to be re-emitted when the topology change and not only
when graphics shaders are emitted.

This fixes spec@nv_primitive_restart@primitive-restart-* with Zink
when shader object is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28179>
 2024-03-15 09:26:33 +00:00
Samuel Pitoiset
ccf894f29c radv: fix RADV_PERFTEST=dmashaders with ESO 
Update the shader upload sequence when individual shaders are bound
to fix that.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28154>
 2024-03-15 08:10:59 +00:00
Samuel Pitoiset
dd0b4f05ad radv: add helpers to bind the GS copy shader and the RT prolog 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28154>
 2024-03-15 08:10:59 +00:00
Friedrich Vock
cc61409ea6 radv: Only enable SEs that the device reports 
Matches PAL behavior.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28195>
 2024-03-15 07:31:34 +00:00
Rhys Perry
ec892c4d2b aco: don't reuse misaligned attribute destination VGPRs in VS prologs 
Since we split misaligned attributes, we could overwrite one of these
VGPRs in the middle of loading the attribute.

For example:
   v_add_u32_e32 v4, vcc, s7, v1
   s_waitcnt lgkmcnt(0)
   buffer_load_dword v4, v4, s[32:35], 0 idxen
   buffer_load_dword v5, v4, s[32:35], 0 idxen offset:4
can overwrite the vertex index in the load of the first component.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
 2024-03-14 15:30:12 +00:00
Rhys Perry
df7024bcdd radv,aco: allow VS prologs to increase VGPR usage 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27920>
 2024-03-14 15:30:12 +00:00
Samuel Pitoiset
1a20942f6a radv: fix wave32 support with ESO 
For example when RADV_PERFTEST=gewave32 is used, the vgt shader key
was incorrect.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
 2024-03-14 14:56:45 +00:00
Samuel Pitoiset
e1c73db01c radv: rework generating vgt_shader_key for pipelines 
This new helper will also be used for ESO.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
 2024-03-14 14:56:45 +00:00
Samuel Pitoiset
c6485f560d radv: determine radv_vgt_shader_key::has_ngg_xxx with the last VGT shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28151>
 2024-03-14 14:56:44 +00:00
Samuel Pitoiset
9ccbd459c6 radv: fix determining if PrimId is used for merged shaders compiled separately 
For ESO when TES and GS are compiled separately,
BREAK_WAVE_AT_EOI/IA_SWITCH_ON_EOI must be enabled if the GS uses
PrimID.

This fixes
tests/spec/arb_tessellation_shader/execution/gs-primitiveid-instanced.shader_test
on RDNA2 when shader object is enabled with Zink.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28149>
 2024-03-14 14:34:19 +00:00
Guilherme Gallo
4350c7cb30 radv/ci: Update xfiles based on nightly run 
Refer to:
- https://gitlab.freedesktop.org/mesa/mesa/-/pipelines/1125483
- https://gitlab.freedesktop.org/mesa/mesa/-/jobs/56167363

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28145>
 2024-03-14 13:53:45 +00:00
Lynne
ee476f3eda radv/av1: limit profile and bit depth to supported values 
Same as with other codecs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28143>
 2024-03-13 02:20:59 +00:00
Marek Olšák
e589833ee1 ac/llvm: fix SSBO bounds checking by using raw instead of struct opcodes 
Setting vindex != NULL (even if it's 0) selects a struct.buffer.load opcode,
which causes LLVM to look for "index * stride + offset" in voffset and
moves "index" to vindex (i.e. not 0 anymore), but the bounds checking
(OOB_SELECT) is set to ignore vindex. Setting vindex = NULL selects
a raw.buffer.load opcode.

Fixes: 6b573c00c9 - ac/nir: use ac_build_buffer_load() for SSBO load operations
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10794

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28119>
 2024-03-12 23:00:00 +00:00
Alyssa Rosenzweig
a6123a80da nir/opt_shrink_vectors: shrink some intrinsics from start 
If the backend supports it, intrinsics with a component() are straightforward to
shrink from the start. Notably helps vectorized I/O.

v2: add an option for this and enable only on grown up backends, because some
backends ignore the component() parameter.

RADV GFX11:
Totals from 921 (1.16% of 79439) affected shaders:
Instrs: 616558 -> 615529 (-0.17%); split: -0.30%, +0.14%
CodeSize: 3099864 -> 3095632 (-0.14%); split: -0.25%, +0.11%
Latency: 2177075 -> 2160966 (-0.74%); split: -0.79%, +0.05%
InvThroughput: 299997 -> 298664 (-0.44%); split: -0.47%, +0.02%
VClause: 16343 -> 16395 (+0.32%); split: -0.01%, +0.32%
SClause: 10715 -> 10714 (-0.01%)
Copies: 24736 -> 24701 (-0.14%); split: -0.37%, +0.23%
PreVGPRs: 30179 -> 30173 (-0.02%)
VALU: 353472 -> 353439 (-0.01%); split: -0.03%, +0.02%
SALU: 40323 -> 40322 (-0.00%)
VMEM: 25353 -> 25352 (-0.00%)

AGX:

total instructions in shared programs: 2038217 -> 2038049 (<.01%)
instructions in affected programs: 10249 -> 10081 (-1.64%)

total alu in shared programs: 1593094 -> 1592939 (<.01%)
alu in affected programs: 7145 -> 6990 (-2.17%)

total fscib in shared programs: 1589254 -> 1589102 (<.01%)
fscib in affected programs: 7217 -> 7065 (-2.11%)

total bytes in shared programs: 13975666 -> 13974722 (<.01%)
bytes in affected programs: 65942 -> 64998 (-1.43%)

total regs in shared programs: 592758 -> 591187 (-0.27%)
regs in affected programs: 6936 -> 5365 (-22.65%)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> (v1)
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28004>
 2024-03-12 18:17:17 +00:00
Rhys Perry
a977a51a21 radv: stop using 5/8 component SSBO stores 
These apparently work, but I'm not sure they were supposed to.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
 2024-03-12 17:23:29 +00:00
Rhys Perry
cc7e3efc7c radv: don't advertise DGC with LLVM 
The meta shaders for this feature don't compile with LLVM because of 5/8
component SSBO stores. I'm not sure this was ever expected to work.

This seemed to break vkd3d-proton.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28108>
 2024-03-12 17:23:29 +00:00
Marek Olšák
82aca689c1 ac: use the gfx11 shadowed register tables for gfx11.5 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
 2024-03-11 23:36:55 +00:00
Marek Olšák
62d360c287 amd/registers: add correct gfx11.x enums for BINNING_MODE 
Fixes: ced3fbbcf9 - amd/registers: add gfx11.json

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27943>
 2024-03-11 23:36:55 +00:00
Friedrich Vock
4c35828933 radv,driconf: Remove active accel struct workaround 
Now unused and enabled by default.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28077>
 2024-03-11 17:08:09 +00:00
Friedrich Vock
217072d25f radv/rt: Force active leaves for every updateable accel struct 
We can't rely on games getting updates right. To avoid adding
workarounds for tons of games, be more robust by default.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28077>
 2024-03-11 17:08:09 +00:00