Konstantin Seurer 6095b70f85 radv/rt: Use 32-bit offsets for load_sbt_entry ... Totals from 82 (18.06% of 454) affected shaders: MaxWaves: 820 -> 821 (+0.12%) Instrs: 2765694 -> 2766338 (+0.02%); split: -0.08%, +0.10% CodeSize: 14751988 -> 14735464 (-0.11%); split: -0.13%, +0.01% VGPRs: 8464 -> 8448 (-0.19%) SpillSGPRs: 454 -> 512 (+12.78%) Latency: 19368679 -> 19344967 (-0.12%); split: -0.21%, +0.09% InvThroughput: 5354427 -> 5346317 (-0.15%); split: -0.24%, +0.08% VClause: 100183 -> 100331 (+0.15%); split: -0.02%, +0.17% SClause: 66584 -> 66590 (+0.01%); split: -0.02%, +0.03% Copies: 237008 -> 238684 (+0.71%); split: -0.53%, +1.23% Branches: 113344 -> 113386 (+0.04%); split: -0.00%, +0.04% PreSGPRs: 6141 -> 6194 (+0.86%) PreVGPRs: 7916 -> 7880 (-0.45%) Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27725>		2024-03-19 17:03:28 +00:00
..
addrlib	amd: update addrlib	2024-03-09 16:56:56 +00:00
ci	radeonsi/ci: udpate expected failures	2024-03-18 14:03:46 +00:00
common	ac: Improve context roll readability	2024-03-19 16:08:14 +00:00
compiler	aco: use small_vec as Block::edge_vec for predecessors and successors	2024-03-19 13:06:58 +00:00
drm-shim	amd: Use align64 instead of ALIGN for 64 bit value parameter	2024-01-03 22:02:17 +00:00
llvm	ac/llvm: fix SSBO bounds checking by using raw instead of struct opcodes	2024-03-12 23:00:00 +00:00
registers	amd/registers: add correct gfx11.x enums for BINNING_MODE	2024-03-11 23:36:55 +00:00
vpelib	amd/vpelib: Add UID for 3d Lut and control logic	2024-02-06 14:55:02 +00:00
vulkan	radv/rt: Use 32-bit offsets for load_sbt_entry	2024-03-19 17:03:28 +00:00
meson.build	amd,radeonsi: add libvpe	2023-12-01 00:23:38 +00:00