Commit graph

55884 commits

Author SHA1 Message Date
Kenneth Graunke
57405605a8 i965: Actually claim to support MSAA on Broadwell.
We need to advertise 8x, 4x, and 2x multisamples.  Previously, we only
claimed to support 0/1 samples.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:43:22 -08:00
Kenneth Graunke
4af8c95783 i965: Update physical width/height munging for 2x IMS MSAA.
I can't find any documentation to explain what ought to be done here, so
I simply guessed based on the pattern I observed in the 4x/8x cases.
It appears to work, but it could be totally wrong.

I was able to find the Sandybridge PRM quote from the comments in the
latest documentation: Shared Functions > 3D Sampler > Multisampled
Surface Behavior.  However, it only mentions 4x MSAA - not even 8x.

After a substantial amount more digging, I was able to find a second
page (incorrectly tagged) which confirmed the formulas in our code for
8x MSAA.  However, that page didn't mention 2x MSAA at all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:43:22 -08:00
Kenneth Graunke
51145a24f7 i965: Enable smooth points when multisampling without point sprites.
According to the "Point Multisample Rasterization" of the OpenGL
specification (3.0 or later), smooth points are supposed to be enabled
implicitly when multisampling, regardless of the GL_POINT_SMOOTH flag.

However, if GL_POINT_SPRITE is enabled, you get square points no matter
what.  Core contexts always enable point sprites, so this effectively
makes smooth points go away, even in the case of multisampling.

Fixes Piglit's EXT_framebuffer_multisample/point-smooth tests.
(Yes, that's right folks, we actually have Piglit tests for this.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:43:22 -08:00
Kenneth Graunke
a3d70580b5 i965: Thwack multisample enable bit in 3DSTATE_RASTER.
The meaning and effects of this bit are surprisingly complicated.

See Rasterization > Windower > Multisampling > Multisample ModesState.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:43:22 -08:00
Kenneth Graunke
0c5873c9b9 i965: Only use the SIMD16 program for per-sample shading on Broadwell.
This restriction carries forward from earlier platforms.  The code is
ported straight from gen7_wm_state.c.

v2: Actually do it right.
v3: Add missing _NEW_MULTISAMPLE bit (caught by Eric).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:42:54 -08:00
Kenneth Graunke
61d7ea4b16 i965: Set "Position XY Offset Select" bits in 3DSTATE_PS on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:42:16 -08:00
Kenneth Graunke
01c42b2be6 i965: Add missing sample shading bits to Gen8's 3DSTATE_PS_EXTRA.
v2: Also set the "oMask Present to Render Target" bit, which is required
    for shaders that write oMask.  Otherwise the hardware won't expect
    the extra data.

v3: Add missing _NEW_MULTISAMPLE (caught by Eric).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:42:02 -08:00
Kenneth Graunke
77c37ed74b i965/fs: Implement FS_OPCODE_SET_OMASK on Broadwell.
I made a few changes which I think simplify the code a bit compared to
the Gen7 implementation, but which are largely pointless.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:39:41 -08:00
Kenneth Graunke
5476da79f8 i965/fs: Implement FS_OPCODE_SET_SAMPLE_ID on Broadwell.
Largely cut and paste from Gen7; it works the same way.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:39:41 -08:00
Kenneth Graunke
80c4edfc27 i965: Disable MCS on Broadwell for now.
v2: Add a perf_debug() message to remind us to come back to this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:39:21 -08:00
Kenneth Graunke
4eba0d124d i965: Use gen7_surface_msaa_bits in Broadwell SURFACE_STATE code.
We already set the number of samples, but were missing the MSAA layout
mode.  Reusing gen7_surface_msaa_bits makes it easy to set both.

This also lets us drop the Gen8 surface_num_multisamples function.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:35:54 -08:00
Kenneth Graunke
6eeae17c02 i965: Use ffs() for sample counting in gen7_surface_msaa_bits().
The enumerations are just log2(num_samples) shifted by 3, which we can
easily compute via ffs().

This also makes it reusable for Broadwell, which has 2x MSAA.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:35:53 -08:00
Kenneth Graunke
2ed5824a5d i965: Simplify Broadwell's 3DSTATE_MULTISAMPLE sample count handling.
These enumerations are simply log2 of the number of multisamples shifted
by a bit, so we can calculate them using ffs() in a lot less code.

Suggested by Eric Anholt.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:35:32 -08:00
Ian Romanick
7700c73cf4 glsl: Silence "type qualifiers ignored on function return type" warning
The const in

   const unsigned foo(void);

is meaningless.  Removing it silences this warning:

src/glsl/ast_to_hir.cpp:1802:56: warning: type qualifiers ignored on function return type [-Wignored-qualifiers]

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-02-19 15:08:50 -08:00
Ian Romanick
2c85fd5a96 glsl: Only warn for macro names containing __
From page 14 (page 20 of the PDF) of the GLSL 1.10 spec:

    "In addition, all identifiers containing two consecutive underscores
     (__) are reserved as possible future keywords."

The intention is that names containing __ are reserved for internal use
by the implementation, and names prefixed with GL_ are reserved for use
by Khronos.  Names simply containing __ are dangerous to use, but should
be allowed.

Per the Khronos bug mentioned below, a future version of the GLSL
specification will clarify this.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "9.2 10.0 10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Cc: Tapani Pälli <lemody@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71870
Bugzilla: Khronos #11702
2014-02-19 15:08:50 -08:00
Ian Romanick
0bd7892630 glcpp: Only warn for macro names containing __
Section 3.3 (Preprocessor) of the GLSL 1.30 spec (and later) and the
GLSL ES spec (all versions) say:

    "All macro names containing two consecutive underscores ( __ ) are
    reserved for future use as predefined macro names. All macro names
    prefixed with "GL_" ("GL" followed by a single underscore) are also
    reserved."

The intention is that names containing __ are reserved for internal use
by the implementation, and names prefixed with GL_ are reserved for use
by Khronos.  Since every extension adds a name prefixed with GL_ (i.e.,
the name of the extension), that should be an error.  Names simply
containing __ are dangerous to use, but should be allowed.  In similar
cases, the C++ preprocessor specification says, "no diagnostic is
required."

Per the Khronos bug mentioned below, a future version of the GLSL
specification will clarify this.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "9.2 10.0 10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Darius Spitznagel <d.spitznagel@goodbytez.de>
Cc: Tapani Pälli <lemody@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71870
Bugzilla: Khronos #11702
2014-02-19 15:08:50 -08:00
Francisco Jerez
8928d7860a i965/fs: Allocate the param_size array dynamically.
Useful because the total number of uniform components might exceed
MAX_UNIFORMS * 4 in some cases because of the image metadata we'll be
passing as push constants.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 19:03:56 +01:00
Francisco Jerez
eef710fc53 i965/fs: Use a separate variable to keep track of the last uniform index seen.
Like the VEC4 back-end does.  It will make dynamic allocation of the
param_size array easier in a future commit.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 19:03:56 +01:00
Rob Clark
9186cd39d4 freedreno: tweak ringbuffer sizes/count
Since we are now consuming two ringbuffers at a time, we probably want a
pool larger than 4.. but we don't need each individual ringbuffer to be
so large, so offset the pool size increase by reducing rb size.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-19 12:02:57 -05:00
Rob Clark
5993723471 freedreno/a3xx/compiler: scheduling/legalize fixes
It seems the write-after-read hazard that applies to texture fetch
instructions, also applies to sfu instructions.

Also, cat5/cat6 instructions do not have a (ss) bit, so in these
cases we need to insert a dummy nop instruction with (ss) bit set.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-02-19 12:01:26 -05:00
Francisco Jerez
bbf8239f92 i965: Have brw_imm_vf4() take the vector components as integer values.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:56:57 +01:00
Francisco Jerez
51b00c5cb9 i965: Add helper function to find out the signedness of a register type.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:56:57 +01:00
Francisco Jerez
560f10e573 i965/vec4: Use swizzle() in the ARB_vertex_program code.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
8797ccf3fa i965/fs: Use offset() in the ARB_fragment_program code.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
6f56d5dc60 i965/fs: Remove fs_reg::retype.
There doesn't seem to be any reason for it to be a method, and it's
surprising that the expression 'reg.retype(t)' doesn't retype its
object but rather it creates a temporary with the new type.  Use
'retype(reg, t)' instead.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
3b03273275 i965/vec4: Trivial improvements to the with_writemask() function.
Add assertion that the register is not in the HW_REG or IMM file,
calculate the conjunction of the old and new mask instead of replacing
the old [consistent with the behavior of brw_writemask(), causes no
functional changes right now], make it static inline to let the
compiler do a slightly better job at optimizing things, and shorten
its name.

v2: Assert that the new writemask is not zero to avoid undefined
    hardware behaviour.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
42b226ef82 i965: Make sure that backend_reg::type and brw_reg::type are consistent for fixed regs.
And define non-mutating helper functions to retype fixed and normal
regs with a common interface.  At some point we may want to get rid of
::fixed_hw_reg completely and have fixed regs use the normal register
data members (e.g. backend_reg::reg to select a fixed GRF number,
src_reg::swizzle to store the swizzle, etc.), I have the feeling that
this is not the last headache we're going to get because of the
multiple ways to represent the same thing and the different register
interface depending on the file a register is stored in...

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
98306e727b i965/vec4: Add non-mutating helper functions to modify src_reg::swizzle and ::negate.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
2337820d49 i965: Add non-mutating helper functions to modify the register offset.
Yes, we could avoid having four copies of essentially the same code by
using templates here.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
af25addcd0 i965/vec4: Fix off-by-one register class overallocation.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
a32817f3c2 i965: Unify fs_generator:: and vec4_generator::mark_surface_used as a free function.
This way it can be used anywhere.  I need it from the visitor.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:25 +01:00
Francisco Jerez
ae8b066da5 i965: Move up duplicated fields from stage-specific prog_data to brw_stage_prog_data.
There doesn't seem to be any reason for nr_params, nr_pull_params,
param, and pull_param to be duplicated in the stage-specific
subclasses of brw_stage_prog_data.  Moving their definition to the
common base class will allow some code sharing in a future commit, the
removal of brw_vec4_prog_data_compare and brw_*_prog_data_free, and
the simplification of the stage-specific brw_*_prog_data_compare.

Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 16:27:22 +01:00
Francisco Jerez
7f00c5f1a3 i965/vec4: Add constructor of src_reg from a fixed hardware reg.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2014-02-19 15:10:57 +01:00
Kenneth Graunke
98e048cf32 i965: Enable fast depth clears.
They work fine now, too.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
7023786417 i965: Enable HiZ on Broadwell.
It appears to work fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
8cad1c115a i965: Implement HiZ resolves on Broadwell.
Broadwell's 3DSTATE_WM_HZ_OP packet makes this much easier.

Instead of programming the whole pipeline, we simply have to emit the
depth/stencil packets, a state override, and a pipe control.  Then
arrange for the state to be put back.  This is easily done from a single
function.

v2: Use minify(mt->logical_{width,height}0, level) in 3DSTATE_WM_HZ_OP
    instead of intel_mipmap_level's width/height fields.  Those were
    based on the physical width/height, and thus wrong for MSAA buffers.
    Eric also deleted those fields.

v3: Use 0xFFFF as the sample mask regardless of what the user set (as
    this operation is unrelated); set the drawing rectangle to the
    miplevel being operated on, rather than the whole surface; remove
    unnecessary MAX2(..., 1) around mt->logical_depth0 (all suggested
    by Eric Anholt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
82711611cf i965: Refactor Gen8 depth packet emission.
The existing code followed the vtable function signature, which is not a
great fit: many of the parameters are unused, and the function still
inspects global state, making it less reusable.

This patch refactors the depth buffer packet emission code into a new
function which takes exactly the parameters it needs, and which uses no
global state.  It then makes the existing vtable function call the new
one.

Ideally, we would remove the vtable function, and clean up that
interface.  But that can happen once HiZ is working.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
67f073b91c i965: Add #defines for the 3DSTATE_WM_HZ_OP packet's contents.
We're going to need these to implement HiZ.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
577fdf1f48 i965: Bump generation check in code to disable HiZ at LODs > 0.
Broadwell's "HiZ Resolve" operation still has the restriction that the
rectangle primitive must be 8x4 aligned.  So I believe we still need
this.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:17 -08:00
Kenneth Graunke
a5d2eb6b98 i965: Program 3DSTATE_HIER_DEPTH_BUFFER properly on Broadwell.
HiZ buffers still don't exist, but when they do, we'll set them up.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:16 -08:00
Kenneth Graunke
09d9a8913e i965: Pull format conversion logic out of brw_depthbuffer_format.
brw_depthbuffer_format is not very reusable at the moment, since it
uses global state (ctx->DrawBuffer) to access a particular depth buffer.

For HiZ on Broadwell, I need a function which simply converts the
formats.  However, at least one existing user of brw_depthbuffer_format
really wants the existing interface.  So, I've created a new function.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-02-19 01:46:16 -08:00
Chia-I Wu
4695f64895 egl: clarify what _eglInitResource does
It is a helper called from the initializers of its subclasses.
2014-02-19 13:08:54 +08:00
Chia-I Wu
dc97e54d97 Revert "egl: Unhide functionality in _eglInitContext()"
This reverts commit 1456ed85f0.
_eglInitResource can and is supposed to be called on subclass objects.

Acked-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-02-19 13:08:52 +08:00
Chia-I Wu
924490a747 Revert "egl: Unhide functionality in _eglInitSurface()"
This reverts commit 498d10e230.
_eglInitResource can and is supposed to be called on subclass objects.

Acked-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
2014-02-19 13:08:44 +08:00
Kenneth Graunke
c593ad6e46 i965: Bump MaxTexMbytes from 1GB to 1.5GB.
Even with the other limits raised, TestProxyTexImage would still reject
textures > 1GB in size.  This is an artificial limit; nothing prevents
us from having a larger texture.  I stayed shy of 2GB to avoid the
larger-than-aperture situation.

For 3D textures, this raises the effective limit:
 - RGBA8:   645 -> 738
 - RGBA16:  512 -> 586
 - RGBA32F: 406 -> 465

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-18 18:59:24 -08:00
Kenneth Graunke
6c04423153 i965: Bump GL_MAX_CUBE_MAP_TEXTURE_SIZE to 8192.
Gen4+ supports 8192x8192 cube maps.  Ivybridge and later can actually
support 16384, but that would place GL_MAX_CUBE_MAP_TEXTURE_SIZE above
GL_MAX_TEXTURE_SIZE, which seems like a bad idea.

(Unfortunately, we can't bump GL_MAX_TEXTURE_SIZE to 16384 without
causing regressions due to awful W-tiled stencil buffer interactions.)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-18 18:59:18 -08:00
Kenneth Graunke
06b047ebc7 i965: Bump MAX_3D_TEXTURE_SIZE to 2048.
It's highly unlikely that there will be enough memory in the system to
allocate enough space for this, but we should still expose the hardware
limit.  It's what the Intel Windows driver does, and it seems most other
vendors do likewise.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74130
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-18 18:58:57 -08:00
Sinclair Yeh
6c9d6898fd Prevent zero sized wl_egl_window
It is illegal to create or resize a window to zero (or negative) width
and/or height.  This patch prevents such a request from happening.
2014-02-18 14:12:11 -08:00
Anuj Phogat
03597cf802 glsl: Fix condition to generate shader link error
GL_ARB_ES2_compatibility doesn't say anything about shader linking
when one of the shaders (vertex or fragment shader) is absent. So,
the extension shouldn't change the behavior specified in GLSL
specification.

Tested the behavior on proprietary linux drivers of NVIDIA and AMD.
Both of them allow linking a version 100 shader program in OpenGL
context, when one of the shaders is absent.

Makes following Khronos CTS tests to pass:
successfulcompilevert_linkprogram.test
successfulcompilefrag_linkprogram.test

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-18 11:07:09 -08:00
Anuj Phogat
6bd2472a8b mesa: Add GL_TEXTURE_CUBE_MAP_ARRAY to legal_get_tex_level_parameter_target()
Fixes failing Khronos CTS test packed_depth_stencil_init.test

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-02-18 11:07:09 -08:00