fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-27 01:50:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965/fs: Implement FS_OPCODE_SET_OMASK on Broadwell.

Browse source 
I made a few changes which I think simplify the code a bit compared to
the Gen7 implementation, but which are largely pointless.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke 2014-02-10 15:46:56 -08:00
parent 5476da79f8
commit 77c37ed74b
2 changed files with 38 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -720,6 +720,9 @@ private:
struct brw_reg index,
struct brw_reg offset);
void generate_mov_dispatch_to_flags(fs_inst *ir);
void generate_set_omask(fs_inst *ir,
struct brw_reg dst,
struct brw_reg sample_mask);
void generate_set_sample_id(fs_inst *ir,
struct brw_reg dst,
struct brw_reg src0,

36
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
View file

@ -596,6 +596,40 @@ gen8_fs_generator::generate_set_simd4x2_offset(fs_inst *ir,
MOV_RAW(retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
}
/**
* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
* (when mask is passed as a uniform) of register mask before moving it
* to register dst.
*/
void
gen8_fs_generator::generate_set_omask(fs_inst *inst,
struct brw_reg dst,
struct brw_reg mask)
{
assert(dst.type == BRW_REGISTER_TYPE_UW);
if (dispatch_width == 16)
dst = vec16(dst);
if (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
mask.width == BRW_WIDTH_8 &&
mask.hstride == BRW_HORIZONTAL_STRIDE_1) {
mask = stride(mask, 16, 8, 2);
} else {
assert(mask.vstride == BRW_VERTICAL_STRIDE_0 &&
mask.width == BRW_WIDTH_1 &&
mask.hstride == BRW_HORIZONTAL_STRIDE_0);
}
unsigned save_exec_size = default_state.exec_size;
default_state.exec_size = BRW_EXECUTE_8;
gen8_instruction *mov = MOV(dst, retype(mask, dst.type));
gen8_set_mask_control(mov, BRW_MASK_DISABLE);
default_state.exec_size = save_exec_size;
}
/**
* Do a special ADD with vstride=1, width=4, hstride=0 for src1.
*/
@ -998,7 +1032,7 @@ gen8_fs_generator::generate_code(exec_list *instructions)
break;
case FS_OPCODE_SET_OMASK:
assert(!"XXX: Missing Gen8 scalar support for SET_OMASK");
generate_set_omask(ir, dst, src[0]);
break;
case FS_OPCODE_SET_SAMPLE_ID: