Commit graph

221052 commits

Author SHA1 Message Date
Jesse Natalie
2c99dc8a18 d3d12: Don't allow CPU storage for huge buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40896>
2026-04-13 12:33:20 +00:00
Danylo Piliaiev
889f71f71a tu: Add tracepoints for clear/copy/blit/lrz ops
There shouldn't be many per frame, so it won't be spammy.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40788>
2026-04-13 11:29:48 +00:00
Georg Lehmann
8d52c3840b radv: do not remove point size variable
This is now done later on lowered io.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40907>
2026-04-13 10:58:01 +00:00
Georg Lehmann
e1e476e618 radv: remove point size in lowered io
We only need to deal with the fixed function last vertex stage case,
for prior stages nir_opt_varyings is enough.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40907>
2026-04-13 10:58:01 +00:00
Jose Maria Casanova Crespo
2b6b859a22 v3dv: defer tile_alloc creation in meta TLB ops
Some checks are pending
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Remove the allocate_tile_state_now parameter from v3dv_job_start_frame().
So v3dv_job_allocate_tile_state() is explicitly called after
job_emit_binning_flush() as we know the value of job->draw_count instead
of using always 0.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40554>
2026-04-13 10:31:21 +00:00
Jose Maria Casanova Crespo
69880047d8 v3dv: use shared v3d_tile_alloc_sizes() and 128B initial blocks
Replace the inline tile_alloc/TSDA sizing in v3dv_job_allocate_tile_state()
with a call to the new v3d_tile_alloc_sizes() helper. This switches from
64B to 128B initial tile alloc blocks (avoiding overflow for simple draws)
and from a flat 512KB headroom to a draw-proportional formula.

Set tile_allocation_initial_block_size and tile_allocation_block_size
in all TILE_BINNING_MODE_CFG emissions and update the
TILE_LIST_INITIAL_BLOCK_SIZE packets to match.

Benchmarked on RPi5 (V3D 7.1) with GfxBench Vulkan Aztec Ruins at
1920x1040. Average tile_alloc BO size dropped 75% (535 KB to 132 KB)
with 20% fewer OOM events (521 to 417) and no FPS regression.

This avoids exhausting GPU memory when multiple blit or fill jobs
are batched in the same command buffer, with a huge reduction of
the memory footprint avoiding the 512 KB of the tile_alloc per batched
job.

Reviewed-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40554>
2026-04-13 10:31:21 +00:00
Jose Maria Casanova Crespo
35efce437e v3d: use shared v3d_tile_alloc_sizes() and 128B initial blocks
Replace the inline tile_alloc/TSDA sizing in alloc_tile_state() with a
call to the new v3d_tile_alloc_sizes() helper. This switches from 64B
to 128B initial tile alloc blocks (avoiding overflow for simple draws)
and from a flat 512KB headroom to a draw-proportional formula.

Set tile_allocation_initial_block_size and tile_allocation_block_size
in all TILE_BINNING_MODE_CFG emissions and update the
TILE_LIST_INITIAL_BLOCK_SIZE packet to match.

Reviewed-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40554>
2026-04-13 10:31:20 +00:00
Jose Maria Casanova Crespo
47fa229605 broadcom/common: add tile alloc block size macros and sizing helper
Add V3D_TILE_ALLOC_INITIAL_BLOCK_SIZE = 128 and
V3D_TILE_ALLOC_OVERFLOW_BLOCK_SIZE = 64 to v3d_limits.h.

Corresponding _ENUM macros provide the 2-bit hardware encoding for the
TILE_BINNING_MODE_CFG packets.

The previous implicit 64B initial blocks were too small: a single draw
call emits ~88 bytes of per-tile BCL state, immediately overflowing
into continuation blocks. 128B initial blocks avoid the first
continuation allocation for simple single-draw passes.

Add v3d_tile_alloc_sizes() to v3d_util with the full tile alloc BO and
TSDA sizing logic. This uses the 128B initial blocks and tile_alloc
becomes proportional to the number of draws and size of the initial
blocks allocation with the cap of the previous fixed allocation. So
jobs with 0 or 1 drawcalls (blits/fills) reduce their headroom
dramatically.

The draw-proportional formula replaces a flat 512 KB continuation pool:

  headroom = MIN2((tiles_size * draw_count) / 2, 512 KB)

Benchmarked on RPi5 (V3D 7.1) against GfxBench GL tests and
apitrace replays at 1080p. Tile-alloc memory reduction versus the
flat 512 KB headroom (taking into account 256kb kernel alloc per OOM):

  GfxBench (5 benchmarks): -45% to -70% reduction, OOM at or below baseline
  Apitrace (19 traces): -4% to -77%  reduction on 20/24 traces

No FPS regressions observed on any workload.

Reviewed-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40554>
2026-04-13 10:31:20 +00:00
Jakob Sinclair
4542982062 pan/compiler: Use SHADDX instruction for i64 add
For Valhall, use SHADDX instruction for 64-bit integer addition instead
of lowering it to 32-bit operations. The instruction sequence for doing
it in 32-bit costs 3 cycles but SHADDX only takes 2 cycles to perform.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40841>
2026-04-13 10:04:22 +00:00
Jakob Sinclair
d4b843c24d pan/compiler: Fix style formatting in lower_split_src
This is just a formatting patch.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40841>
2026-04-13 10:04:22 +00:00
Jakob Sinclair
245460bda5 pan/compiler: Do not assume split 64-bit registers in va_mark_last
va_mark_last currently expects 64-bit registers to always be split in
two, this commit changes it to check first if a 64-bit register is split
or not.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40841>
2026-04-13 10:04:22 +00:00
David Rosca
c9a8dcd63c radeonsi/vcn: Don't force balance encode preset with sao on VCN5
This is only needed for VCN4 and older.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40766>
2026-04-13 09:45:54 +00:00
David Rosca
e8bce7ec47 radeonsi/vcn: Remove encode op_preset overrides
The only difference is HIGH_QUALITY on VCN4+ and forcing BALANCE
with sao on VCN2+.

Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40766>
2026-04-13 09:45:54 +00:00
Wujian Sun
2e340d63d2 mesa: Fix inconsistent multisampled CopyTexImage checks
According to the GL_EXT_multisampled_render_to_texture specification,
copy operations should be allowed when the extension is supported.

Previously, glCopyTexImage* would unconditionally fail with
GL_INVALID_OPERATION when copying from any multisampled framebuffer
(samples > 0), even when using render-to-texture attachments.

Fixes: d7b9da2673 ("mesa/main: fix artifacts with GL_EXT_multisampled_render_to_texture")

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Wujian Sun <wujian.sun_1@nxp.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40863>
2026-04-13 09:18:58 +00:00
Eric Guo
c415134454 panfrost: disable round_to_nearest_even for NEAREST samplers
When round_to_nearest_even is enabled with NEAREST filtering, texture
coordinates near texel boundaries (e.g. 0.9999999404) can be incorrectly
rounded up to the next texel instead of being floor()'d.

According to OpenCL spec section 8.2, for CLK_FILTER_NEAREST:
  i = address_mode((int)floor(u))

Backport-to: *
Signed-off-by: Eric Guo <eric.guo@nxp.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40912>
2026-04-13 08:38:55 +00:00
Yogesh Mohan Marimuthu
21047e61a5 winsys/amdgpu: call userq wait ioctl only once
Some checks are pending
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Allocate to hold 256 wait fences. Since there is only one queue per
per ip per process, the idea is that there won't be app or windowing system
that would have large number of job dependencies / wait fences.

If there is an app that has wait fences greater than 256, there won't
be corruption issues since kernel will wait for the extra fences.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40698>
2026-04-13 05:15:43 +00:00
Yogesh Mohan Marimuthu
5df6fc5481 winsys/amdgpu: pointers to be NULL if num 0 for kernel ioctl
From https://docs.kernel.org/process/botching-up-ioctls.html, Kernel
ioctl expects pointers are NULL if number of pointers variable is 0.

Kernel ioctl can have checks for these and return failure causing
the driver to fail.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40698>
2026-04-13 05:15:43 +00:00
Karol Herbst
58d45725c7 rusticl/device: Fix reporting of global memory on mixed memory devices
Some checks are pending
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AMD APUs are hitting this case where they have very small discrete VRAM,
but a lot of staging memory, which can be used additionally.

Fixes: 7487ac2046 ("rusticl/device: support query_memory_info to retrieve available memory")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30123>
2026-04-12 21:58:40 +00:00
Karol Herbst
97a137ac88 rusticl/kernel: implement CL_KERNEL_GLOBAL_WORK_SIZE for custom devices
Apparently we are supposed to support this on custom devices.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30123>
2026-04-12 21:58:40 +00:00
Karol Herbst
97ca375f51 radeonsi: properly report unified memory on APUs
This helps rusticl to properly advertise available global memory on APUs.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30123>
2026-04-12 21:58:40 +00:00
Pavel Ondračka
64b0b83c9a r300/ci: update expectations
Some checks are pending
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40906>
2026-04-12 18:49:23 +00:00
Pavel Ondračka
ba6736fa2b r300/ci: rv380 piglit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40906>
2026-04-12 18:49:23 +00:00
Georg Lehmann
21bdc7105d radv: clarify that copy prop is required for correctness after D16 opt
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/14854
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40871>
2026-04-12 17:54:48 +00:00
Georg Lehmann
51ba9b956a aco: use no contract/reassoc instead of exact
Some checks are pending
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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:29 +00:00
Georg Lehmann
b0194d0416 aco/tests: fix med3 NaN tests
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:28 +00:00
Georg Lehmann
5269c6d422 zink/ntv: seperate float control2 exact bits
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Georg Lehmann
5231c924ea intel/peephole_fma: use nir_fp_no_contract instead of exact
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Georg Lehmann
d2d86b83fb nir/opt_reassociate: use nir_fp_no_reassoc instead of exact
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Georg Lehmann
6549b993e6 nir/algebraic: actually seperate contract and inexact
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Georg Lehmann
ed50cf29f3 spirv: map float control2 to fine grained nir flags instead of exact
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Georg Lehmann
a42ac8dec6 nir: split exact bit into no_contract/reassoc/transform
Just like float control2.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40872>
2026-04-12 17:10:27 +00:00
Konstantin Seurer
db38d1a98c radv/bvh: Prefer selecting quads as the first pair of a HW node
Is a single triangle is selected, it can be the case that the next iteration
can't merge any pair with the triangle. In that case, the HW node with a
single triangle will not have the highest hw_node_index, triggering an
assert.

Fixes: c18a7d0 ("radv: Emit compressed primitive nodes on GFX12")
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39655>
2026-04-12 17:53:05 +02:00
Danylo Piliaiev
9e56c7bd8f tu: Support transfer commands for R64 formats
Some checks are pending
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CTS tests that require transfer commands:
   dEQP-VK.robustness.*r64*
   dEQP-VK.api.image_clearing.*.r64*
   dEQP-VK.image.extend_operands_spirv1p4.r64_*
   dEQP-VK.image.nontemporal_operand.r64_*
   dEQP-VK.image.queue_transfer.*.r64_

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Danylo Piliaiev
5b87bbfad3 tu: Support EXT_shader_image_atomic_int64
Required for SM6.6 in vkd3d-proton and used in a number of UE5 titles.
From descriptor side R64 images are R32G32_UINT, and to get storage_descriptor
we have to move early-return if format doesn't support rendering after
storage_descriptor setup.

Passes vkd3d-proton test:
test_shader_sm66_64bit_atomics

CTS tests:
dEQP-VK.image.atomic_operations.*.r64*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
0eab11b67f ir3: add support for 64-bit image atomics
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
b7b66d3efd ir3: add support for r64u?i image loads/stores
Add a NIR pass to lower these to r32g32u loads/stores, which is our
descriptor format.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
bc4edc79dd ir3: support isam with less than 4 components
This currently doesn't happen yet but we want to support load_image with
lass than 4 components in the future.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
bd69573c34 ir3: allow imm src0 (IBO) on bindless atomics
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Job Noorman
b8437e30bf nir/lower_atomics: add support for bindless_image_atomic
Initial data is loaded via bindless_image_load, atomic swap via
bindless_image_atomic_swap.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39932>
2026-04-11 19:46:13 +00:00
Janne Grunau
e0c07c42e0 hk: ci: Handle more spurious wsi CTS timeouts/fails
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The timeout in
dEQP-VK.wsi.wayland.incremental_present.scale_none.fifo.identity.opaque.incremental_present
is already fixed in vulkan-cts-1.4.5.1.
dEQP-VK.wsi.xcb.maintenance1.present_{fences,modes}.* are known flakes,
see commit 9ec387efb1 ("panvk: advertise wsi maintenance extensions").

Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40861>
2026-04-11 19:23:45 +00:00
Janne Grunau
8469c3f512 hk: ci: Skip timing out wsi xlib tests
These tests likely timeout on all drivers, see the linked issue for details.

Link: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15116
Signed-off-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40861>
2026-04-11 19:23:45 +00:00
Konstantin Seurer
01156c0697 vulkan: Init all update scratch at once
Some checks are pending
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Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39752>
2026-04-11 13:04:39 +00:00
Konstantin Seurer
411e23d389 vulkan: Remove bvh_state
This will allow passing the whole array to the driver.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39752>
2026-04-11 13:04:39 +00:00
Konstantin Seurer
50b1becdde vulkan: move internal_node_count to vk_acceleration_structure_build_state
Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39752>
2026-04-11 13:04:38 +00:00
Konstantin Seurer
63daa4e731 vulkan: Request less scratch space for lbvh
It is fine if prior passes write to the region so the memory can be
reused.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39752>
2026-04-11 13:04:38 +00:00
Konstantin Seurer
4ab113b7eb vulkan: Add helper for dispatching BVH build stages
The number of flag combination grows exponentially.

Reviewed-by: Natalie Vock <natalie.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39752>
2026-04-11 13:04:38 +00:00
Vinson Lee
2443f3608a d3d12: Fix MinGW cross-build error in resource_state_if_promoted
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When cross-compiling with MinGW, d3d12_resource_state.cpp fails to
compile with:

  d3d12_resource_state.cpp:161:83: error: call to non-'constexpr'
  function 'D3D12_RESOURCE_STATES operator|(D3D12_RESOURCE_STATES,
  D3D12_RESOURCE_STATES)'
    161 |       D3D12_RESOURCE_STATE_ALL_SHADER_RESOURCE |
        |       D3D12_RESOURCE_STATE_COPY_SOURCE | D3D12_RESOURCE_STATE_COPY_DEST;
        |       ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  In file included from /usr/share/mingw-w64/include/minwindef.h:163,
                   from /usr/share/mingw-w64/include/windef.h:9,
                   from /usr/share/mingw-w64/include/windows.h:69,
                   from /usr/share/mingw-w64/include/rpc.h:16,
                   from /usr/share/mingw-w64/include/unknwn.h:7,
                   from ../subprojects/DirectX-Headers-1.0/include/wsl/winadapter.h:6,
                   from ../src/gallium/drivers/d3d12/d3d12_common.h:29,
                   from ../src/gallium/drivers/d3d12/d3d12_bufmgr.h:31,
                   from ../src/gallium/drivers/d3d12/d3d12_resource_state.cpp:24:
  ../subprojects/DirectX-Headers-1.0/include/directx/d3d12.h:3540:1:
  note: 'D3D12_RESOURCE_STATES operator|(D3D12_RESOURCE_STATES,
  D3D12_RESOURCE_STATES)' declared here
   3540 | DEFINE_ENUM_FLAG_OPERATORS( D3D12_RESOURCE_STATES )
        | ^~~~~~~~~~~~~~~~~~~~~~~~~~

The DEFINE_ENUM_FLAG_OPERATORS macro in the MinGW winnt.h header
defines operator| for D3D12_RESOURCE_STATES as inline but not
constexpr.  (The DirectX-Headers WSL stubs do define it as constexpr,
but when building with MinGW, windows.h is pulled in via winadapter.h
and its non-constexpr definition wins.)  Calling a non-constexpr
function to initialize a constexpr variable is ill-formed in C++.

Fix by changing static constexpr to static const, which avoids the
constexpr context while still giving the variable static storage
duration.

Fixes: fe48cd7c5a ("d3d12: Allow state promotion for non-simultaneous access textures")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40880>
2026-04-10 23:43:03 -07:00
Gurchetan Singh
f92cfe9a74 gfxstream: additional Goldfish logic for Android builds
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Goldfish needs a non-stub QEMU pipe stream and access
to the goldfish_sync device.

All of this logic may be deleted once qemu over
virtio-gpu is fully enabled.

TEST=run meson2hermetic + m vulkan.ranchu

Reviewed-by: Bo Hu <bohu@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40851>
2026-04-11 01:11:45 +00:00
Mel Henning
c7ab501171 nvk: Disable zcull save/restore regions for now
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
The issues with this are proving to be difficult to solve. Turn it off
for now until we have a proper fix.

Fixes: c24963d8da ("nvk: Enable zcull for VK_ATTACHMENT_LOAD_OP_LOAD")
Acked-by: Mary Guillemard <mary@mary.zone>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40894>
2026-04-10 22:20:58 +00:00
Collabora's Gfx CI Team
d15e4274f6 Uprev Piglit to 11ce9eb56edb00e6a7702d13168cc827ce5e0cbd
d0a16eee4f...11ce9eb56e

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40427>
2026-04-10 21:21:52 +00:00