Commit graph

16066 commits

Author SHA1 Message Date
Dave Airlie
2bb2e6a6e3 xorg: port to new compat API.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2012-06-06 15:22:50 +01:00
Brian Paul
3a62e8bcac translate_test: add support for half floats
Fixes assertion reported in
https://bugs.freedesktop.org/show_bug.cgi?id=44519
but there's still failing cases.
2012-06-06 07:55:59 -06:00
Tom Stellard
d4942eb9fa radeon/llvm: Remove obselete hooks for the ConvertToISA pass
We can't remove this pass yet, because we need it to convert AMDIL
registers in BRANCH* instructions, but we don't need it for
instruction conversion any more.
2012-06-06 13:46:04 -04:00
Tom Stellard
edceed1b9a radeon/llvm: Remove AMDIL MOVE* instructions 2012-06-06 13:46:04 -04:00
Tom Stellard
f81e4663a7 radeon/llvm: Add isMov() to AMDILInstrInfo
This enables the CFGStructurizer to work without the AMDIL::MOV*
instructions.
2012-06-06 13:46:04 -04:00
Tom Stellard
1777c99bff radeon/llvm: Remove deadcode from the AMDILISelLowering class 2012-06-06 13:46:03 -04:00
Tom Stellard
8cc9b463de radeon/llvm: Don't lower RETURN to S_ENDPGM on SI
Instead create an S_ENDPGM instruction in the CodeEmitter and emit
it after all the other instructions.
2012-06-06 13:46:03 -04:00
Tom Stellard
de7366701d radeon/llvm: Remove AMDIL VCREATE* instructions
This obsoletes the AMDGPULowerInstruction pass.
2012-06-06 13:46:03 -04:00
Tom Stellard
8d53ddb375 radeon/llvm: Remove AMDIL LOADCONST* instructions
This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
2012-06-06 13:46:03 -04:00
Marcin Slusarz
17e047242e nouveau: fix scratch buffer leak
...and create common function for destroying nouveau_context
2012-06-05 23:58:43 +02:00
Marcin Slusarz
3232a86efe nv50: fix nv50_stream_output_state leak 2012-06-05 23:58:43 +02:00
Marcin Slusarz
cfa7cb991c nv50: fix symbol table memory leak 2012-06-05 23:58:43 +02:00
Tom Stellard
0ebf2318b3 radeon/llvm: Fix VTX_READ patterns
The VTX_READ instructions were using the ADDRParam ComplexPattern which
allows a load instruction's offset to be a register, but VTX_READ
instructions can only handle an immediate offset.

Also, the load_param pattern fragment had an erroneous return true;
statement that was causing it to match the wrong load instructions.
2012-06-01 16:52:26 -04:00
Tom Stellard
c108831d44 radeon/llvm: Emit 2 bytes for vertex fetch offsets 2012-06-01 16:52:26 -04:00
Tom Stellard
85a68814ee radeon/llvm: Only use indirect (vertex fetch) parameters for kernels
Kernel parameters can only be retrieved via vertex fetchs.  Direct
parameters (i.e parameters stored in the constant buffer) are not
supported yet.
2012-06-01 16:52:26 -04:00
Tom Stellard
d6c2d3722d radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructions
Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so
that the CFGStructurizer pass can run without any relying on AMDIL
instructions.
2012-06-01 11:28:11 -04:00
Tom Stellard
65917004d9 radeon/llvm: Change prefix on tablegen files to AMDGPU 2012-06-01 11:28:11 -04:00
Tom Stellard
afea59bf65 radeon/llvm: Remove deadcode from the R600LowerInstructions pass 2012-06-01 11:28:10 -04:00
Tom Stellard
883a0af53a radeon/llvm: Remove AMDIL GLOBALSTORE* instructions 2012-06-01 11:28:10 -04:00
Tom Stellard
f2781271c7 radeon/llvm: Remove AMDIL GLOBALLOAD* instructions 2012-06-01 11:28:10 -04:00
Adam Rak
6a829a1b72 r600g: compute support for evergreen
Tom Stellard:
  - Updated for gallium interface changes
  - Fixed a few bugs:
    + Set the loop counter
    + Calculate the correct number of pipes
  - Added hooks into the LLVM compiler
2012-06-01 11:28:10 -04:00
Tom Stellard
46a13b3b11 clover: Add function for building a clover::module for non-TGSI targets v6
v2:
  -Separate IR type and LLVM triple
  -Do the OpenCL C->LLVM IR and linking steps for all PIPE_SHADER_IR
   types.

v3:
  - Coding style fixes
  - Removed compatibility code for LLVM < 3.1
  - Split build_module_llvm() into three functions:
    compile(), link(), and build_module_llvm()

v4:
  - Use struct pipe_compute_program

v5:
  - Don't malloc memory for struct pipe_llvm_program

v6:
  - Fix serialization of llvm bytecode

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:28:10 -04:00
Tom Stellard
f2606413ec gallium: Add struct pipe_llvm_program_header v3
This structure is used as a header that precedes LLVM bytecode programs
that are passed to the drivers.

v2:
  - s/pipe_compute_program/pipe_llvm_program/

v3:
  - Rename to struct pipe_llvm_program_header
  - Drop the char * prog member

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:28:10 -04:00
Tom Stellard
741463e18d clover: Remove target argument from compile_program_tgsi()
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:28:10 -04:00
Tom Stellard
d724190bce clover: Add constructors to some of the module classes v3
This is for the llvm code that can't use extended initializers.

v2:
  - Use const references for vector arguments
  - Move constructor defs before data members
  - Initialize all values in the default constructors

v3:
  - Fix typo
2012-06-01 11:28:09 -04:00
Tom Stellard
5cc08efe8f clover: Add necessary flags to libclllvm_la_CXXFLAGS
$(LLVM_CFLAGS) for LLVM defines
-DLIBCLC_PATH for libclc path
-DCLANG_RESOURCE_DIR for clang includes
$(DEFINES) for -DHAVE_LLVM
2012-06-01 11:28:09 -04:00
Tom Stellard
7a6b5d42d8 clover: Link to the necessary LLVM and Clang libs 2012-06-01 11:28:09 -04:00
Tom Stellard
613323b256 clover: Add a function for retrieving a device's preferred ir v3
A device now has two function for getting information about the IR
it needs to return.

ir_format() => returns the preferred IR
ir_target() => returns the triple for the target that is understood by
                 clang/llvm.

v2:
  - renamed ir_target() to ir_format()
  - renamed llvm_triple() to ir_target()

v3:
  - Remove unnecessary include
  - Do proper conversion from std::vector<char> to std::string

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:28:09 -04:00
Francisco Jerez
c4c51153bc gallium/compute: Add PIPE_COMPUTE_CAP_IR_TARGET v4
v2: Tom Stellard
  - Update CAP description

v3: Tom Stellard
  - TGSI targets should pass an empty string for this CAP.

v4: Tom Stellard
  - TGSI targets can ignore this CAP.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:27:53 -04:00
Tom Stellard
1d118a2a76 gallium: Add PIPE_SHADER_IR_LLVM to enum pipe_shader_ir v2
v2:
  - s/PIPE_SHADER_IR_LLVM_R600/PIPE_SHADER_IR_LLVM/

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2012-06-01 11:26:57 -04:00
Brian Paul
8009fca501 svga: fix saturated TEX instructions
TEX instructions can't do saturation.  Do the TEX into a temp reg w/out
saturation, then do a MOV_SAT.

Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
2012-05-31 12:54:04 -06:00
Brian Paul
dff36e900c scons: add code to generate the various GL API files
This fixes recent build breakage when we began building the generated
API files from xml as part of the normal build process.

Fixes http://bugs.freedesktop.org/show_bug.cgi?id=50475
2012-05-31 09:40:35 -06:00
Brian Paul
185ed21058 draw: simplify index buffer specification
Replace draw_set_index_buffer() and draw_set_mapped_index_buffer() with
draw_set_indexes() which simply takes a pointer and an index size.
2012-05-31 09:40:35 -06:00
Marcin Slusarz
8924133627 nv50: hook up forgotten short constant buffer upload method
Fixes crash in xorg st.
2012-05-29 20:24:45 +02:00
Tom Stellard
83169900fb radeon/llvm: Update and fix some comments 2012-05-29 11:59:01 -04:00
Tom Stellard
89ece086bc radeonsi: Remove use.sgpr* intrinsics, use load instructions instead
We now model loading uses sgpr values with LLVM IR load instructions that
use the USER_SGPR address space.

The definition of the sgpr parameter to the use_sgpr() helper function
in radeonsi_shader.c has changed so that you can pass raw sgpr values
rather than having to divide the sgpr value you want to use by the dword
width of the type you want to load.
2012-05-29 11:55:53 -04:00
Tom Stellard
467f51613e radeonsi: Handle TGSI CONST registers
We now emit LLVM load instructions for TGSI CONST register reads,
which are lowered in the backend to S_LOAD_DWORD* instructions.
2012-05-29 11:55:52 -04:00
Tom Stellard
32b83e0366 radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction body
This function was causing compile errors in the tablegen'd code for
some intrinsic definitions.  I don't think we really need this function,
so I'm removing the function body just as a temporary solution.  I'll
look into removing the entire AMDILIntrinsicInfo class later.
2012-05-29 11:55:52 -04:00
Tom Stellard
49fb99bd13 radeon/llvm: Remove AMDILTargetMachine 2012-05-29 11:55:52 -04:00
Christoph Bumiller
94a25b216b nouveau: unreference fences on resource destruction 2012-05-29 17:00:20 +02:00
Christoph Bumiller
1a21e36b68 nvc0: optimize blend cso by checking which by-RT data actually differs
Can save about 200 bytes of command buffer space.
2012-05-29 17:00:18 +02:00
Christoph Bumiller
f09ee76c98 nvc0: don't upload UCPs if the shader doesn't use them 2012-05-29 17:00:15 +02:00
Christoph Bumiller
79eed0d224 nvc0/ir: allow 64-bit constant loads on nve4
Looks like only 128-bit access doesn't work.
2012-05-29 17:00:10 +02:00
Christoph Bumiller
40c224a573 nvc0/ir: fix texture barrier insertion to prevent WAW hazards
Fixes, for instance, object highlighting in Diablo 3 (wine).
2012-05-29 15:01:41 +02:00
Christoph Bumiller
0d818cdacc nvc0/ir: TEX doesn't support JOIN modifier either 2012-05-29 15:01:41 +02:00
Christoph Bumiller
f80c2874ec gallium: add st_api feature mask to prevent advertising MS visuals
v2: use a define for the maximum sample count
v3: also test odd sample counts (r300 supports MS3)

While multisample renderbuffers are supported by mesa, MS visuals
are not, so we need a way to tell dri/st not to advertise them even
if the gallium driver does support multisampled surfaces.

Otherwise applications selecting these non-functional visuals would
run into trouble ...

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-05-29 15:01:41 +02:00
Roy Spliet
6404095fba nv30: Fix generic passing to fragment program in NV34. 2012-05-25 22:42:54 +02:00
Christoph Bumiller
384ef28cb3 nv30: handle user index buffers 2012-05-25 22:42:54 +02:00
Tom Stellard
704eac0916 radeon/llvm: Use a custom inserter for MASK_WRITE 2012-05-25 15:40:59 -04:00
Tom Stellard
4863477e22 radeon/llvm: Use tablegen pattern to lower bitconvert 2012-05-25 15:40:59 -04:00