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radeon/llvm: Change prefix on tablegen files to AMDGPU

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This commit is contained in:
Tom Stellard 2012-05-30 19:23:39 -04:00
parent afea59bf65
commit 65917004d9
17 changed files with 50 additions and 50 deletions
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0
src/gallium/drivers/radeon/AMDIL.td → src/gallium/drivers/radeon/AMDGPU.td
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4
src/gallium/drivers/radeon/AMDIL.h
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@ -105,9 +105,9 @@ extern Target TheAMDGPUTarget;
} // end namespace llvm;
#define GET_REGINFO_ENUM
#include "AMDILGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "AMDILGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
/// Include device information enumerations
#include "AMDILDeviceInfo.h"

2
src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
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@ -71,7 +71,7 @@ private:
bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
// Include the pieces autogenerated from the target description.
#include "AMDILGenDAGISel.inc"
#include "AMDGPUGenDAGISel.inc"
};
} // end anonymous namespace

2
src/gallium/drivers/radeon/AMDILISelLowering.cpp
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@ -38,7 +38,7 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
// Calling Convention Implementation
//===----------------------------------------------------------------------===//
#include "AMDILGenCallingConv.inc"
#include "AMDGPUGenCallingConv.inc"
//===----------------------------------------------------------------------===//
// TargetLowering Implementation Help Functions Begin

2
src/gallium/drivers/radeon/AMDILInstrInfo.cpp
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@ -22,7 +22,7 @@
#include "llvm/Instructions.h"
#define GET_INSTRINFO_CTOR
#include "AMDILGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
using namespace llvm;

2
src/gallium/drivers/radeon/AMDILInstrInfo.h
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@ -18,7 +18,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#define GET_INSTRINFO_HEADER
#include "AMDILGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
namespace llvm {
// AMDIL - This namespace holds all of the target specific flags that

10
src/gallium/drivers/radeon/AMDILIntrinsicInfo.cpp
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@ -21,7 +21,7 @@
using namespace llvm;
#define GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN
AMDILIntrinsicInfo::AMDILIntrinsicInfo(TargetMachine *tm)
@ -35,7 +35,7 @@ AMDILIntrinsicInfo::getName(unsigned int IntrID, Type **Tys,
{
static const char* const names[] = {
#define GET_INTRINSIC_NAME_TABLE
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_NAME_TABLE
};
@ -107,7 +107,7 @@ unsigned int
AMDILIntrinsicInfo::lookupName(const char *Name, unsigned int Len) const
{
#define GET_FUNCTION_RECOGNIZER
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_FUNCTION_RECOGNIZER
AMDGPUIntrinsic::ID IntrinsicID
= (AMDGPUIntrinsic::ID)Intrinsic::not_intrinsic;
@ -132,13 +132,13 @@ AMDILIntrinsicInfo::isOverloaded(unsigned id) const
{
// Overload Table
#define GET_INTRINSIC_OVERLOAD_TABLE
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_OVERLOAD_TABLE
}
/// This defines the "getAttributes(ID id)" method.
#define GET_INTRINSIC_ATTRIBUTES
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_ATTRIBUTES
Function*

2
src/gallium/drivers/radeon/AMDILIntrinsicInfo.h
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@ -22,7 +22,7 @@ namespace llvm {
enum ID {
last_non_AMDIL_intrinsic = Intrinsic::num_intrinsics - 1,
#define GET_INTRINSIC_ENUM_VALUES
#include "AMDILGenIntrinsics.inc"
#include "AMDGPUGenIntrinsics.inc"
#undef GET_INTRINSIC_ENUM_VALUES
, num_AMDIL_intrinsics
};

2
src/gallium/drivers/radeon/AMDILRegisterInfo.cpp
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@ -198,5 +198,5 @@ AMDILRegisterInfo::getStackSize() const
}
#define GET_REGINFO_TARGET_DESC
#include "AMDILGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"

2
src/gallium/drivers/radeon/AMDILRegisterInfo.h
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@ -17,7 +17,7 @@
#include "llvm/Target/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#include "AMDILGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"
// See header file for explanation
namespace llvm

2
src/gallium/drivers/radeon/AMDILSubtarget.cpp
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@ -25,7 +25,7 @@ using namespace llvm;
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDILGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"
AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS ),
mDumpCode(false)

2
src/gallium/drivers/radeon/AMDILSubtarget.h
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@ -22,7 +22,7 @@
#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "AMDILGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"
#define MAX_CB_SIZE (1 << 16)
namespace llvm {

6
src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.cpp
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@ -9,13 +9,13 @@
#include "llvm/Support/TargetRegistry.h"
#define GET_INSTRINFO_MC_DESC
#include "AMDILGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_MC_DESC
#include "AMDILGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"
#define GET_REGINFO_MC_DESC
#include "AMDILGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"
using namespace llvm;

6
src/gallium/drivers/radeon/MCTargetDesc/AMDILMCTargetDesc.h
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@ -24,12 +24,12 @@ extern Target TheAMDGPUTarget;
} // End llvm namespace
#define GET_REGINFO_ENUM
#include "AMDILGenRegisterInfo.inc"
#include "AMDGPUGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "AMDILGenInstrInfo.inc"
#include "AMDGPUGenInstrInfo.inc"
#define GET_SUBTARGETINFO_ENUM
#include "AMDILGenSubtargetInfo.inc"
#include "AMDGPUGenSubtargetInfo.inc"
#endif // AMDILMCTARGETDESC_H

36
src/gallium/drivers/radeon/Makefile
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@ -38,32 +38,32 @@ endif
R600RegisterInfo.td: R600GenRegisterInfo.pl
$(PERL) $^ > $@
AMDILGenRegisterInfo.inc: *.td
$(call tablegen, -gen-register-info, AMDIL.td, $@)
AMDGPUGenRegisterInfo.inc: *.td
$(call tablegen, -gen-register-info, AMDGPU.td, $@)
AMDILGenInstrInfo.inc: *.td
$(call tablegen, -gen-instr-info, AMDIL.td, $@)
AMDGPUGenInstrInfo.inc: *.td
$(call tablegen, -gen-instr-info, AMDGPU.td, $@)
AMDILGenAsmWriter.inc: *.td
$(call tablegen, -gen-asm-writer, AMDIL.td, $@)
AMDGPUGenAsmWriter.inc: *.td
$(call tablegen, -gen-asm-writer, AMDGPU.td, $@)
AMDILGenDAGISel.inc: *.td
$(call tablegen, -gen-dag-isel, AMDIL.td, $@)
AMDGPUGenDAGISel.inc: *.td
$(call tablegen, -gen-dag-isel, AMDGPU.td, $@)
AMDILGenCallingConv.inc: *.td
$(call tablegen, -gen-callingconv, AMDIL.td, $@)
AMDGPUGenCallingConv.inc: *.td
$(call tablegen, -gen-callingconv, AMDGPU.td, $@)
AMDILGenSubtargetInfo.inc: *.td
$(call tablegen, -gen-subtarget, AMDIL.td, $@)
AMDGPUGenSubtargetInfo.inc: *.td
$(call tablegen, -gen-subtarget, AMDGPU.td, $@)
AMDILGenEDInfo.inc: *.td
$(call tablegen, -gen-enhanced-disassembly-info, AMDIL.td, $@)
AMDGPUGenEDInfo.inc: *.td
$(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@)
AMDILGenIntrinsics.inc: *.td
$(call tablegen, -gen-tgt-intrinsic, AMDIL.td, $@)
AMDGPUGenIntrinsics.inc: *.td
$(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@)
AMDILGenCodeEmitter.inc: *.td
$(call tablegen, -gen-emitter, AMDIL.td, $@)
AMDGPUGenCodeEmitter.inc: *.td
$(call tablegen, -gen-emitter, AMDGPU.td, $@)
LOADER_LIBS=$(shell llvm-config --libs bitreader asmparser)
loader: loader.o libradeon.a

18
src/gallium/drivers/radeon/Makefile.sources
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@ -4,15 +4,15 @@ GENERATED_SOURCES := \
R600RegisterInfo.td \
SIRegisterInfo.td \
SIRegisterGetHWRegNum.inc \
AMDILGenRegisterInfo.inc \
AMDILGenInstrInfo.inc \
AMDILGenAsmWriter.inc \
AMDILGenDAGISel.inc \
AMDILGenCallingConv.inc \
AMDILGenSubtargetInfo.inc \
AMDILGenEDInfo.inc \
AMDILGenIntrinsics.inc \
AMDILGenCodeEmitter.inc
AMDGPUGenRegisterInfo.inc \
AMDGPUGenInstrInfo.inc \
AMDGPUGenAsmWriter.inc \
AMDGPUGenDAGISel.inc \
AMDGPUGenCallingConv.inc \
AMDGPUGenSubtargetInfo.inc \
AMDGPUGenEDInfo.inc \
AMDGPUGenIntrinsics.inc \
AMDGPUGenCodeEmitter.inc
CPP_SOURCES := \
AMDIL7XXDevice.cpp \

2
src/gallium/drivers/radeon/R600CodeEmitter.cpp
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@ -654,5 +654,5 @@ uint64_t R600CodeEmitter::getMachineOpValue(const MachineInstr &MI,
}
}
#include "AMDILGenCodeEmitter.inc"
#include "AMDGPUGenCodeEmitter.inc"