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radeon/llvm: Remove obselete hooks for the ConvertToISA pass

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We can't remove this pass yet, because we need it to convert AMDIL
registers in BRANCH* instructions, but we don't need it for
instruction conversion any more.
This commit is contained in:
Tom Stellard 2012-06-05 20:10:31 -04:00
parent edceed1b9a
commit d4942eb9fa
6 changed files with 1 additions and 87 deletions
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3
src/gallium/drivers/radeon/AMDGPUInstrInfo.cpp
View file

@ -29,10 +29,9 @@ MachineInstr * AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction
MachineInstrBuilder newInstr;
MachineRegisterInfo &MRI = MF.getRegInfo();
const AMDGPURegisterInfo & RI = getRegisterInfo();
unsigned ISAOpcode = getISAOpcode(MI.getOpcode());
// Create the new instruction
newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(ISAOpcode));
newInstr = BuildMI(MF, DL, TM.getInstrInfo()->get(MI.getOpcode()));
for (unsigned i = 0; i < MI.getNumOperands(); i++) {
MachineOperand &MO = MI.getOperand(i);

4
src/gallium/drivers/radeon/AMDGPUInstrInfo.h
View file

@ -36,10 +36,6 @@ public:
virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
/// getISAOpcode - This function takes an AMDIL opcode as an argument and
/// returns an equivalent ISA opcode.
virtual unsigned getISAOpcode(unsigned AMDILopcode) const = 0;
/// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
/// MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,

40
src/gallium/drivers/radeon/R600InstrInfo.cpp
View file

@ -61,46 +61,6 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
}
unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const
{
switch (opcode) {
default: return opcode;
case AMDIL::IEQ:
return AMDIL::SETE_INT;
case AMDIL::INE:
return AMDIL::SETNE_INT;
case AMDIL::IGE:
return AMDIL::SETGE_INT;
case AMDIL::MOVE_f32:
case AMDIL::MOVE_i32:
return AMDIL::MOV;
case AMDIL::UGE:
return AMDIL::SETGE_UINT;
case AMDIL::UGT:
return AMDIL::SETGT_UINT;
}
}
unsigned R600InstrInfo::getASHRop() const
{
unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
if (gen < AMDILDeviceInfo::HD5XXX) {
return AMDIL::ASHR_r600;
} else {
return AMDIL::ASHR_eg;
}
}
unsigned R600InstrInfo::getLSHRop() const
{
unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration();
if (gen < AMDILDeviceInfo::HD5XXX) {
return AMDIL::LSHR_r600;
} else {
return AMDIL::LSHR_eg;
}
}
MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF,
unsigned DstReg, int64_t Imm) const
{

4
src/gallium/drivers/radeon/R600InstrInfo.h
View file

@ -41,12 +41,8 @@ namespace llvm {
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
virtual unsigned getISAOpcode(unsigned opcode) const;
bool isTrig(const MachineInstr &MI) const;
unsigned getLSHRop() const;
unsigned getASHRop() const;
virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const;

28
src/gallium/drivers/radeon/SIInstrInfo.cpp
View file

@ -77,34 +77,6 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const
}
}
MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const
{
MachineInstr * newMI = AMDGPUInstrInfo::convertToISA(MI, MF, DL);
const MCInstrDesc &newDesc = get(newMI->getOpcode());
/* If this instruction was converted to a VOP3, we need to add the extra
* operands for abs, clamp, omod, and negate. */
if (getEncodingType(*newMI) == SIInstrEncodingType::VOP3
&& newMI->getNumOperands() < newDesc.getNumOperands()) {
MachineInstrBuilder builder(newMI);
for (unsigned op_idx = newMI->getNumOperands();
op_idx < newDesc.getNumOperands(); op_idx++) {
builder.addImm(0);
}
}
return newMI;
}
unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
{
switch (AMDILopcode) {
//XXX We need a better way of detecting end of program
case AMDIL::MOVE_f32: return AMDIL::V_MOV_B32_e32;
default: return AMDILopcode;
}
}
MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const
{

9
src/gallium/drivers/radeon/SIInstrInfo.h
View file

@ -42,15 +42,6 @@ public:
/// number of bytes.
unsigned getEncodingBytes(const MachineInstr &MI) const;
/// convertToISA - Convert the AMDIL MachineInstr to a supported SI
///MachineInstr
virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
DebugLoc DL) const;
/// getISAOpcode - This function takes an AMDIL opcode as an argument and
/// returns an equivalent SI opcode.
virtual unsigned getISAOpcode(unsigned AMDILopcode) const;
virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
int64_t Imm) const;