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radeon/llvm: Use a custom inserter for MASK_WRITE

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This commit is contained in:
Tom Stellard 2012-05-25 12:53:22 -04:00
parent 4863477e22
commit 704eac0916
4 changed files with 36 additions and 34 deletions
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15
src/gallium/drivers/radeon/AMDGPUInstructions.td
View file

@ -49,16 +49,7 @@ def FP_ONE : PatLeaf <
[{return N->isExactlyValue(1.0);}]
>;
let isCodeGenOnly = 1 in {
def MASK_WRITE : AMDGPUShaderInst <
(outs),
(ins GPRF32:$src),
"MASK_WRITE $src",
[]
>;
let isPseudo = 1, usesCustomInserter = 1 in {
let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in {
class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
(outs rc:$dst),
@ -81,9 +72,7 @@ class FNEG <RegisterClass rc> : AMDGPUShaderInst <
[(set rc:$dst, (fneg rc:$src0))]
>;
} // End isPseudo = 1, hasCustomInserter = 1
} // End isCodeGenOnly = 1
} // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
/* Generic helper patterns for intrinsics */
/* -------------------------------------- */

12
src/gallium/drivers/radeon/R600ISelLowering.cpp
View file

@ -139,6 +139,18 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
AMDIL::R600_TReg32RegClass.getRegister(RegIndex));
break;
}
case AMDIL::MASK_WRITE:
{
unsigned maskedRegister = MI->getOperand(0).getReg();
assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
MachineOperand * def = defInstr->findRegisterDefOperand(maskedRegister);
def->addTargetFlag(MO_FLAG_MASK);
// Return early so the instruction is not erased
return BB;
}
case AMDIL::STORE_OUTPUT:
{
int64_t OutputIndex = MI->getOperand(1).getImm();

32
src/gallium/drivers/radeon/R600Instructions.td
View file

@ -538,16 +538,6 @@ def TEX_SAMPLE_C_G : R600_TEX <
[]
>;
def KILP : Pat <
(int_AMDGPU_kilp),
(MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
>;
def KIL : Pat <
(int_AMDGPU_kill R600_Reg32:$src0),
(MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
>;
/* Helper classes for common instructions */
class MUL_LIT_Common <bits<32> inst> : R600_3OP <
@ -1072,6 +1062,17 @@ def CLAMP_R600 : CLAMP <R600_Reg32>;
def FABS_R600 : FABS<R600_Reg32>;
def FNEG_R600 : FNEG<R600_Reg32>;
let usesCustomInserter = 1 in {
def MASK_WRITE : AMDGPUShaderInst <
(outs),
(ins R600_Reg32:$src),
"MASK_WRITE $src",
[]
>;
} // End usesCustomInserter = 1
let isPseudo = 1 in {
def LOAD_VTX : AMDGPUShaderInst <
@ -1088,6 +1089,17 @@ def LOAD_VTX : AMDGPUShaderInst <
// ISel Patterns
//===----------------------------------------------------------------------===//
// KIL Patterns
def KILP : Pat <
(int_AMDGPU_kilp),
(MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO)))
>;
def KIL : Pat <
(int_AMDGPU_kill R600_Reg32:$src0),
(MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0)))
>;
// SGT Reverse args
def : Pat <
(selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),

11
src/gallium/drivers/radeon/R600LowerInstructions.cpp
View file

@ -204,17 +204,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
break;
}
case AMDIL::MASK_WRITE:
{
unsigned maskedRegister = MI.getOperand(0).getReg();
assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
MachineInstr * defInstr = MRI->getVRegDef(maskedRegister);
MachineOperand * def = defInstr->findRegisterDefOperand(maskedRegister);
def->addTargetFlag(MO_FLAG_MASK);
/* Continue so the instruction is not erased */
continue;
}
case AMDIL::ULT:
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_UINT))
.addOperand(MI.getOperand(0))