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radeon/llvm: Remove AMDIL GLOBALSTORE* instructions
This commit is contained in:
Tom Stellard
parent
f2781271c7
commit
883a0af53a
4 changed files with 36 additions and 77 deletions
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@ -779,7 +779,6 @@ let Predicates = [Has32BitPtr] in {
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// Store Memory Operations
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//===----------------------------------------------------------------------===//
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defm GLOBALTRUNCSTORE : GTRUNCSTORE<"!global trunc store">;
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defm GLOBALSTORE : STORE<"!global store" , global_store>;
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defm LOCALTRUNCSTORE : LTRUNCSTORE<"!local trunc store">;
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defm LOCALSTORE : STORE<"!local store" , local_store>;
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defm PRIVATETRUNCSTORE : PTRUNCSTORE<"!private trunc store">;
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@ -1069,7 +1068,6 @@ let Predicates = [Has64BitPtr] in {
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// Store Memory Operations
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//===----------------------------------------------------------------------===//
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defm GLOBALTRUNCSTORE64 : GTRUNCSTORE64<"!global trunc store">;
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defm GLOBALSTORE64 : STORE64<"!global store" , global_store>;
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defm LOCALTRUNCSTORE64 : LTRUNCSTORE64<"!local trunc store">;
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defm LOCALSTORE64 : STORE64<"!local store" , local_store>;
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defm PRIVATETRUNCSTORE64 : PTRUNCSTORE64<"!private trunc store">;
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@ -146,6 +146,29 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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return BB;
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}
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case AMDIL::RAT_WRITE_CACHELESS_eg:
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{
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// Convert to DWORD address
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unsigned NewAddr = MRI.createVirtualRegister(
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AMDIL::R600_TReg32_XRegisterClass);
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unsigned ShiftValue = MRI.createVirtualRegister(
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AMDIL::R600_TReg32RegisterClass);
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// XXX In theory, we should be able to pass ShiftValue directly to
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// the LSHR_eg instruction as an inline literal, but I tried doing it
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// this way and it didn't produce the correct results.
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::MOV), ShiftValue)
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.addReg(AMDIL::ALU_LITERAL_X)
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.addImm(2);
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::LSHR_eg), NewAddr)
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.addOperand(MI->getOperand(1))
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.addReg(ShiftValue);
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode()))
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.addOperand(MI->getOperand(0))
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.addReg(NewAddr);
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break;
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}
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case AMDIL::STORE_OUTPUT:
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{
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int64_t OutputIndex = MI->getOperand(1).getImm();
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@ -50,6 +50,7 @@ def MEMrr : Operand<iPTR> {
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}
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def ADDRParam : ComplexPattern<i32, 2, "SelectADDRParam", [], []>;
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def ADDRDWord : ComplexPattern<i32, 1, "SelectADDRDWord", [], []>;
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class R600_ALU {
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@ -164,13 +165,12 @@ def COND_LE : PatLeaf <
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case ISD::SETLE: return true;}}}]
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>;
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class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
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string asm> :
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InstR600ISA <outs, ins, asm, []>
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class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
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dag ins, string asm, list<dag> pattern> :
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InstR600ISA <outs, ins, asm, pattern>
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{
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bits<7> RW_GPR;
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bits<7> INDEX_GPR;
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bits<4> RAT_ID;
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bits<2> RIM;
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bits<2> TYPE;
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@ -186,7 +186,7 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, dag outs, dag ins,
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bits<1> BARRIER;
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/* CF_ALLOC_EXPORT_WORD0_RAT */
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let Inst{3-0} = RAT_ID;
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let Inst{3-0} = rat_id;
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let Inst{9-4} = rat_inst;
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let Inst{10} = 0; /* Reserved */
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let Inst{12-11} = RIM;
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@ -772,9 +772,12 @@ class TRIG_HELPER_r700 <InstR600 trig_inst>: Pat <
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let Predicates = [isEG] in {
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def RAT_WRITE_CACHELESS_eg :
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EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr,
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R600_TReg32_X:$index_gpr, i32imm:$rat_id), "">
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let usesCustomInserter = 1 in {
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def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
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(ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr),
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"RAT_WRITE_CACHELESS_eg $rw_gpr, $index_gpr",
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[(global_store (i32 R600_TReg32_X:$rw_gpr), R600_TReg32_X:$index_gpr)]>
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{
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let RIM = 0;
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/* XXX: Have a separate instruction for non-indexed writes. */
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@ -791,6 +794,8 @@ def RAT_WRITE_CACHELESS_eg :
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let BARRIER = 1;
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}
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} // End usesCustomInserter = 1
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class VTX_READ_eg <int buffer_id, list<dag> pattern> : InstR600ISA <
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(outs R600_TReg32_X:$dst),
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(ins MEMxi:$ptr),
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@ -39,12 +39,6 @@ namespace {
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void lowerFLT(MachineInstr &MI);
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void calcAddress(const MachineOperand &ptrOp,
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const MachineOperand &indexOp,
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unsigned indexReg,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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public:
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R600LowerInstructionsPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TM(tm),
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@ -99,47 +93,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
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}
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*/ /* XXX: This is an optimization */
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case AMDIL::GLOBALSTORE_i32:
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case AMDIL::GLOBALSTORE_f32:
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{
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MachineOperand &ptrOperand = MI.getOperand(1);
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MachineOperand &indexOperand = MI.getOperand(2);
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unsigned rwReg =
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MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
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unsigned byteIndexReg =
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MRI->createVirtualRegister(&AMDIL::R600_TReg32RegClass);
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unsigned shiftReg =
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MRI->createVirtualRegister(&AMDIL::R600_TReg32RegClass);
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unsigned indexReg =
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MRI->createVirtualRegister(&AMDIL::R600_TReg32_XRegClass);
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/* Move the store value to the correct register class */
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::COPY), rwReg)
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.addOperand(MI.getOperand(0));
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/* Calculate the address in the RAT */
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calcAddress(ptrOperand, indexOperand, byteIndexReg, MBB, I);
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MOV), shiftReg)
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.addReg(AMDIL::ALU_LITERAL_X)
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.addImm(2);
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/* XXX: Check GPU family */
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BuildMI(MBB, I, MBB.findDebugLoc(I),
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TII->get(AMDIL::LSHR_eg), indexReg)
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.addReg(byteIndexReg)
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.addReg(shiftReg);
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/* XXX: Check GPU Family */
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BuildMI(MBB, I, MBB.findDebugLoc(I),
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TII->get(AMDIL::RAT_WRITE_CACHELESS_eg))
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.addReg(rwReg)
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.addReg(indexReg)
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.addImm(0);
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break;
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}
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case AMDIL::ILT:
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BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_INT))
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.addOperand(MI.getOperand(0))
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@ -195,23 +148,3 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
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}
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return false;
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}
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void R600LowerInstructionsPass::calcAddress(const MachineOperand &ptrOp,
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const MachineOperand &indexOp,
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unsigned indexReg,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const
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{
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/* Optimize the case where the indexOperand is 0 */
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if (indexOp.isImm() && indexOp.getImm() == 0) {
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assert(ptrOp.isReg());
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BuildMI(MBB, I, MBB.findDebugLoc(I),
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TII->get(AMDIL::COPY), indexReg)
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.addOperand(ptrOp);
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} else {
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BuildMI(MBB, I, MBB.findDebugLoc(I),
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TII->get(AMDIL::ADD_INT), indexReg)
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.addOperand(indexOp)
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.addOperand(ptrOp);
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}
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}
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