Commit graph

201479 commits

Author SHA1 Message Date
Erik Faye-Lund
29cf4608db panfrost: avoid accidental aliasing
We already have a variable call "alignment" here, and aliasing it
breaks things. Whoops, let's rename the variable to page_size to
avoid this.

Fixes: 22985caf3f ("panfrost: sanity-check alignment")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34156>
(cherry picked from commit 1471279203)
2025-04-02 11:04:13 +02:00
Robert Mader
82304cad79 gallivm: Re-add check for passmgr before disposing it
In can be NULL, but on LLVM >= 15 lp_passmgr_dispose() is
a no-op.

Fixes: 47cd0eee26 (gallivm: create a pass manager wrapper.)

Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34312>
(cherry picked from commit c0ec35bb42)
2025-04-02 11:04:13 +02:00
Rebecca Mckeever
42b6bd48b7 panvk: Remove lower_tg4_broadcom_swizzle from panvk_preprocess_nir()
We are already applying the .bagr swizzle in bifrost_preprocess_nir(), so
remove lower_tg4_broadcom_swizzle from nir_lower_tex_options in
panvk_preprocess_nir to avoid applying the swizzle twice.

Fixes: 4050697a8f ("panvk: So more nir_lower_tex before descriptor lowering")

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34033>
(cherry picked from commit f450807b68)
2025-04-02 11:04:13 +02:00
Jordan Justen
98530340ca intel/dev: Add BMG 0xe211 PCI ID
Backport-to: 25.0
Ref: bspec 68090
Ref: https://patchwork.freedesktop.org/series/146769/
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34249>
(cherry picked from commit d3ec467031)
2025-04-02 11:04:13 +02:00
Dave Airlie
cd8715440a gallivm: check for avx512vbmi and tell LLVM the correct answer.
There are some CPUs out there which don't have vbmi and do have
other avx512 and mesa crashes on those with illegal instructions.

This was reported to Red Hat support.

Cc: mesa-stable
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34282>
(cherry picked from commit 5d6d167a7c)
2025-04-02 11:04:13 +02:00
Pierre-Eric Pelloux-Prayer
c8f9b803fa radeonsi: use composed swizzle in cdna_emu_make_image_descriptor
Otherwise the state swizzle is ignored.

Fixes: 139bc6b813 ("radeonsi: use common build buffer descriptor helpers")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34241>
(cherry picked from commit 7e2c3be454)
2025-04-02 11:04:13 +02:00
Pierre-Eric Pelloux-Prayer
ae02c9a2d5 ac/nir: fix nir_metadata value of ac_nir_lower_image_opcodes
This pass can insert new blocks so 'nir_metadata_control_flow' is not
preserved.

Fixes: eaf98b1422 ("ac/nir: implement image opcode emulation for CDNA, enable it in radeonsi")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34241>
(cherry picked from commit 785df1b980)
2025-04-02 11:04:13 +02:00
Samuel Pitoiset
ffa6fd4bee radv: do not trigger FCE or FMASK decompress on compute queue
A pipeline barrier which contains an image layout transition like
COLOR_ATTACHMENT_OPTIMAL -> TRANSFER_DST_OPTIMAL on compute queue
would just hang. Such a barrier is useless in practice but it's legal.

Prevent GPU hangs by skipping FCE or FMASK_DECOMPRESS when it's not
on the graphics queue.

Fixes dEQP-VK.synchronization2.layout_transition.compute_transition*.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34231>
(cherry picked from commit 086f529bbe)
2025-04-02 11:04:13 +02:00
Trigger Huang
1c85e781ce radeonsi: Fix perfcounter start event in si_pc_emit_start
The original typo caused performance counters to send STOP events
instead of START, leading to incorrect profiling data.

Fixes: 1a1138817c ("radeonsi: add a new PM4 helper radeon_event_write")

Signed-off-by: Trigger Huang <Trigger.Huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34236>
(cherry picked from commit f03b385d4b)
2025-04-02 11:04:13 +02:00
Faith Ekstrand
7d3212729b nvk: Disable 32k images on Pascal A
While we're here, add a comment about why we have this restriction in
the first place since NVK and the proprietary driver are different here.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34281>
(cherry picked from commit 59b01dc764)
2025-04-02 11:04:13 +02:00
Faith Ekstrand
9dd82a2e74 nvk: Use max_image_dimension for maxFramebufferWidth/Height
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34281>
(cherry picked from commit 65d06d91ca)
2025-04-02 11:04:13 +02:00
Faith Ekstrand
79f960cb1d vulkan/wsi: Signal buffer memory object when blitting
When we're using the PRIME path and using vkCmdCopyImageToBuffer to copy
to a linear image, the buffer memory is what's shared with the window
system.  For legacy drivers that depend on memory signaling via
wsi_memory_signal_submit_info, we need to tell the driver to signal the
buffer memory, not the image memory or else the window system may wait
on a driver-internal buffer and not wait for the copy to complete.

Cc: mesa-stable
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34218>
(cherry picked from commit cf23ffcbae)
2025-04-02 11:04:13 +02:00
Natalie Vock
9fb56e2780 vulkan/bvh: Move first PLOC task_count fetch inside PHASE
Otherwise, the memory fetch is not protected by the global sync and
memory barriers and there is a chance to read a stale (or just wrong)
task count.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34178>
(cherry picked from commit 8b0271050a)
2025-04-02 11:04:13 +02:00
Natalie Vock
0c3b74d562 radv/rt: Flush CP writes from the common BVH framework with INV_L2 on GFX12
a1b05991 ("radv/rt: Flush L2 after writing internal node offset on GFX12")
did this for radv-internal CP writes - we also need to do this for PLOC
sync data initialization which is done in the common framework.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34178>
(cherry picked from commit c1e1d86bd1)
2025-04-02 11:04:13 +02:00
David Rosca
e790a1caa0 frontends/va: Don't ignore rotation and mirror for conversions to RGB
Cc: mesa-stable
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
(cherry picked from commit 51292976fe)
2025-04-02 11:04:12 +02:00
David Rosca
b6f9ccf0e8 gallium/vl: Fix mirror with rotation for compute shaders
The mirror needs to be reversed because the rotation is applied
before the mirroring.

VAAPI docs:
  Mirroring of an image can be performed either along the
  horizontal or vertical axis. It is assumed that the rotation
  operation is always performed before the mirroring operation.

Cc: mesa-stable
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
(cherry picked from commit 962c33cbca)
2025-04-02 11:04:12 +02:00
David Rosca
d56be9adbd gallium/vl: Fix rotation with scaling for compute shaders
Cc: mesa-stable
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34140>
(cherry picked from commit c8a2f0b248)
2025-04-02 11:04:12 +02:00
Robert Mader
09da8e124f llvmpipe: Free dummy_dmabuf on shutdown
In order to stop ASAN from complaining.

Fixes: d21aa86b54 ("llvmpipe: Implement EGL_ANDROID_native_fence_sync")
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34258>
(cherry picked from commit 2034c901cc)
2025-04-02 11:04:12 +02:00
David Rosca
e09a2e808f radeonsi/vce: Support old VCE firmware
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12866
Fixes: 104f9c6654 ("radeonsi/vce: Remove support for FW 50 and older")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34152>
(cherry picked from commit a2b4617c00)
2025-04-02 11:04:12 +02:00
Connor Abbott
e9b6cf708b tu: Fix reported FDM fragment size with multiview
We were never setting has_multiview. It's not actually necessary anyway,
since we can just do the optimization we were trying to do whenever
num_views is 1 instead.

This doesn't affect the actual fragment size, which was already correct,
only gl_FragSizeEXT.

Fixes: 6f2be52487 ("tu, ir3: Handle FDM shader builtins")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33991>
(cherry picked from commit 8864ee7b0f)
2025-04-02 11:04:12 +02:00
Connor Abbott
0df2cf3ae4 tu: Fix size of frag_size_ir3 and frag_offset_ir3 driver params
They are an array, so we have to reserve extra space for extra views.
This bug was being masked by the bug fixed in the next commit.

Fixes: 76e417ca59 ("turnip,ir3/a750: Implement consts loading via preamble")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33991>
(cherry picked from commit 122f2c422a)
2025-04-02 11:04:12 +02:00
Connor Abbott
40babe1efb tu: Fix GMEM offset for multisample layered separate stencil
Fixes a bug uncovered by CTS when enabling GMEM with layered rendering.

Fixes: def56b531c ("tu: Support GMEM with layered rendering and multiview")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34082>
(cherry picked from commit 6cadc1baea)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
f2fa2ea466 nvk: Use the right sample mask for 8x/4pass on Maxwell A
Fixes: 48898c47bf ("nvk: Rework setup of sample masks")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
(cherry picked from commit cbf87e82e8)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
3e475be117 nouveau/mme/fermi: Don't allow STATE and EMIT on the same op
Fixes: 162269f049 ("nouveau/mme: Add Fermi builder")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
(cherry picked from commit 3354c24169)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
c0de23e92e nvk: Fix a Volta check
Fixes: e162c2e78e ("nvk: Use VM_BIND for contiguous heaps instead of copying")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
(cherry picked from commit 79294fb95a)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
c84a792c96 nvk: Free owned_gart_mem correctly
Fixes: fbe171638e ("nvk: add gart forced cmd pool side buffer.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34127>
(cherry picked from commit 90b2137ac5)
2025-04-02 11:04:12 +02:00
Robert Mader
558a7d92d5 llvmpipe: Take offset into account when importing dmabufs
Which is necessary for many common YCbCr formats.

Fixes: d74ea2c117 (llvmpipe: Implement dmabuf handling)
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34240>
(cherry picked from commit 05e7ac6551)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
4aad059de8 nak: Fix a SM check for OpPCnt
This doens't really fix anything as we don't have any nir_loops on
Volta+ but the code was wrong so we should fix it.

Fixes: 9bbc692064 ("nak/nir: Rework CRS handling")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
(cherry picked from commit af9d65e8b8)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
829c728e89 nak: Always copy sources when handling vec/pack/mov ops
It's possible that the source is uniform but the destination is not.  In
this case, we need to insert a copy or else we might accidentally
propagate a uniform into some place we don't expect it.

This fixes a bunch of fp64 KHR-Single-GL46.subgroups.arithmetic.* tests.

Fixes: d09d3f5246 ("nak/from_nir: Emit uniform instructions when !divergent")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
(cherry picked from commit 1d1d79bbaa)
2025-04-02 11:04:12 +02:00
Faith Ekstrand
1fa4455b6e nak: Insert the annotation in the right spot in assign_regs
Fixes: efc4ac0d27 ("nak/sm50: sprinkle OpAnnotate in optimization passes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34201>
(cherry picked from commit 98677294b9)
2025-04-02 11:04:12 +02:00
irql-notlessorequal
ed75778536 hasvk: Fix non-functioning version override.
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27717 accidentally removed the instance check for the drirc option "hasvk_report_vk_1_3_version", rendering it useless.

Re-add the check and expose Vulkan 1.3 if the user asks.

Fixes: 2d575034f2 ("hasvk: switch to use runtime physical device properties infrastructure")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34232>
(cherry picked from commit c0c562cf6e)
2025-04-02 11:04:12 +02:00
Lionel Landwerlin
ba58320a6a anv: limit implict write with drirc
9f32e1a489 meant to amend 1e80a426c2.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9f32e1a489 ("anv/drirc: Add option to control implicit sync on external BOs")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12629
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33587>
(cherry picked from commit a88c9ea192)
2025-04-02 11:04:12 +02:00
Lionel Landwerlin
5ecc1fb189 brw: always write the VUE header
In 35df3925ca ("brw: ensure VUE header writes in HS/DS/GS stages") I
misread the PRMs and thought that the VF would initialize the header.

What actually happens is that the VF does not write valid values in
there and the PRMs explicitly say that the VS shader should overwrite
whatever is in there.

We could avoid writing the header in some cases when no HW is going to
read back the header. For example with rendering disables through
3DSTATE_STREAMOUT::RenderingDisable. But those cases are dynamic and
the compiler is not able to tell. So just always write the header.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 35df3925ca ("brw: ensure VUE header writes in HS/DS/GS stages")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12880
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34211>
(cherry picked from commit 4db4bd1d04)
2025-04-02 11:04:11 +02:00
Paulo Zanoni
9acee7d46b drirc/anv: DiggingGame.exe needs force_vk_vendor=-1
Otherwise, it fails with a message:

  "Assertion failed: IsValidIndex(Index)
   [File:D:\\build\\++UE5\\Sync\\Engine\\Source\\Runtime\\Core\\Public\\Containers\\UnrealString.h]
   [Line: 218] \nString index out of bounds: Index 0 from a string with
   a length of 0"

Thanks to the ProtonDB community for having figured this out and
documented it for us.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12695
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34103>
(cherry picked from commit e72ad49622)
2025-04-02 11:04:11 +02:00
Samuel Pitoiset
88c7326a61 radv/meta: fix color<->depth/stencil image copies
The color format needs to be compatible with depth or stencil. Also
the depth/stencil format was incorrect when it's the source.

Fixes dEQP-VK.api.ds_color_copy.*
and VKD3D_TEST_FILTER=test_copy_texture.

Fixes: d4ff011b12 ("radv: advertise VK_KHR_maintenance8")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34142>
(cherry picked from commit 2c3b9312cc)
2025-04-02 11:04:11 +02:00
Hyunjun Ko
167bcee3b7 vulkan/video: Do byte-alignment when building a h264 slice header
Fixes: ff8de6190 ("vulkan/video: adds a bitstream writer of h264 slice header")
Closes: mesa/mesa#12835

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34094>
(cherry picked from commit c22a635938)
2025-04-02 11:04:11 +02:00
Samuel Pitoiset
6ad9455f43 radv: fix compresed depth/stencil copies on transfer queue
HTILE is always pipe aligned.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
(cherry picked from commit 114fbdc534)
2025-04-02 11:04:11 +02:00
Samuel Pitoiset
7f32247d95 radv: fix bpe for the stencil aspect of depth/stencil copies on transfer queue
Using the bpe of depth+stencil when copying the stencil aspect only
doesn't work.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
(cherry picked from commit 7b15e85b95)
2025-04-02 11:04:11 +02:00
Rhys Perry
b3991dd8fc aco/ra: fix free register counting when moving variables
info.bounds might be smaller than the bounds available for the moved
variables.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Fixes: 626aa7b648 ("aco: workaround GFX9 hardware bug for D16 image instructions")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34158>
(cherry picked from commit 80fef30531)
2025-04-02 11:04:11 +02:00
Lionel Landwerlin
fad1d950f9 anv: disable replication when we don't have both VS/FS stages
Enabling this with shaders compiled separately through pipeline
libraries fails because we currently only enable it for VS and the
associated FS stage ends up with a non compatible VUE map.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34173>
(cherry picked from commit 25a695552a)
2025-04-02 11:04:11 +02:00
Lionel Landwerlin
c89250cd9f anv: fix end of pipe timestamp query writes
Currently trying to use PIPE_CONTROL on blitter/video engines.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12833
Acked-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34095>
(cherry picked from commit 6b6a4cb1e2)
2025-04-02 11:04:11 +02:00
Samuel Pitoiset
7e55a04643 radv: fix creating pipeline binary from the traversal shader
rt_stage_info is NULL.

Fixes: 8802612458 ("radv: advertise VK_KHR_pipeline_binary")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34141>
(cherry picked from commit 29b3d9f0f4)
2025-04-02 11:04:11 +02:00
Job Noorman
cabc8c606f ir3/legalize: take wrmask into account for delay updates
When updating delays, we'd update all dst regs based on reg_elems.
However, when wrmask has gaps, this would update delays for regs that
aren't actually written. Fix this by skipping regs for which the
corresponding wrmask bit is zero.

Note that this wasn't just a performance issue but could result in
illegal code because the delay is reset to zero for tex/sfu
instructions. For example, the following (post-legalization) code was
observed in the wild:

(rpt1)add.f r1.w, (r)r2.w, (r)c3.z
sam.base0 (f32)(w)r2.x, r3.y, s#0, t#1
rcp r2.x, r2.x

Here, the add would result in a required delay for r2.x which would then
be cleared by the sam (even though it doesn't write to it), resulting in
insufficient delay before the rcp.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 61b2bd861f ("ir3: Rewrite nop insertion")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34107>
(cherry picked from commit 84dbd34332)
2025-04-02 11:04:11 +02:00
Timothy Arceri
de5de2ec60 nir: fix uniform cloning helper
glsl allows for ubos to have the same name but different bindings.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Fixes: b47b8d16d9 ("nir: expose reusable linking helpers for cloning uniform loads")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12852
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34138>
(cherry picked from commit 2b2132d2ac)
2025-04-02 11:04:11 +02:00
Timothy Arceri
20e09c3081 mesa: fix potential race condition in with Programs
The call looks up a Program and creates it if it doesn't
already exist. However we weren't locking the hash between looking
up the name and adding it to the hash so it could be possible
another thread also generated the same name.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c91300f ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit 786b8b2d34)
2025-04-02 11:04:11 +02:00
Timothy Arceri
04df661b13 mesa: fix potential race condition in with ATIShaders
The call looks up an ATIShader and creates it if it doesn't
already exist. However we weren't locking the hash between looking
up the name and adding it to the hash so it could be possible
another thread also generated the same name.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c91300f ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit 4c1e4d7b49)
2025-04-02 11:04:11 +02:00
Timothy Arceri
f150c50170 mesa: fix potential race condition in with RenderBuffers
The calls look up a renderbuffer and create it if it doesn't
already exist. However they weren't locking the hash between looking
up the name and adding it to the hash so it could be possible
another thread also generated the same name.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c91300f ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit 0e61d31e9d)
2025-04-02 11:04:11 +02:00
Timothy Arceri
835a355369 mesa: fix potential race conditions in with FrameBuffers
The calls look up a framebuffer and create it if it doesn't
already exist. However they weren't locking the hash between looking
up the name and adding it to the hash so it could be possible
another thread also generated the same name.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c91300f ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit c4ee84f3b6)
2025-04-02 11:04:11 +02:00
Timothy Arceri
4a158b971c mesa: fix reuse of deleted sampler object
Deleting a sampler object will only cause it to be unbound from the
current context. To avoid reusing something that it still bound in
another context we need to check the DeletePending flag first.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c9130 ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit 9bb696588d)
2025-04-02 11:04:11 +02:00
Timothy Arceri
d44e9736d1 mesa: fix potential race condition in with TexObjects
The calls look up a texture object and create it if it doesn't
already exist. However they weren't locking the hash between looking
up the name and adding it to the hash so it could be possible
another thread also generated the same name.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 842c9130 ("mesa: enable GL name reuse by default for all drivers except virgl")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34091>
(cherry picked from commit 95e87f6a6a)
2025-04-02 11:04:11 +02:00