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anv: fix end of pipe timestamp query writes

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Currently trying to use PIPE_CONTROL on blitter/video engines.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12833
Acked-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34095>
(cherry picked from commit 6b6a4cb1e2)
This commit is contained in:
Lionel Landwerlin 2025-03-20 10:04:43 +02:00 • committed by Eric Engestrom
parent 7e55a04643
commit c89250cd9f
2 changed files with 53 additions and 30 deletions
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2
.pick_status.json
View file

@ -3824,7 +3824,7 @@
"description": "anv: fix end of pipe timestamp query writes",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

81
src/intel/vulkan/genX_query.c
View file

@ -72,6 +72,51 @@ emit_query_mi_flush_availability(struct anv_cmd_buffer *cmd_buffer,
}
}
static void
emit_query_mi_availability(struct mi_builder *b,
struct anv_address addr,
bool available)
{
mi_store(b, mi_mem64(addr), mi_imm(available));
}
static void
emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,
struct anv_address addr,
bool available)
{
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData, addr,
available, 0);
}
/* End of pipe availability */
static void
emit_query_eop_availability(struct anv_cmd_buffer *cmd_buffer,
struct anv_address addr,
bool available)
{
switch (cmd_buffer->queue_family->engine_class) {
case INTEL_ENGINE_CLASS_RENDER:
case INTEL_ENGINE_CLASS_COMPUTE:
emit_query_pc_availability(cmd_buffer, addr, available);
break;
case INTEL_ENGINE_CLASS_COPY:
case INTEL_ENGINE_CLASS_VIDEO:
case INTEL_ENGINE_CLASS_VIDEO_ENHANCE:
emit_query_mi_flush_availability(cmd_buffer, addr, available);
break;
default:
unreachable("Invalid engine class");
}
}
VkResult genX(CreateQueryPool)(
VkDevice _device,
const VkQueryPoolCreateInfo* pCreateInfo,
@ -727,28 +772,6 @@ emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_DEPTH_STALL_BIT | (cs_stall_needed ? ANV_PIPE_CS_STALL_BIT : 0));
}
static void
emit_query_mi_availability(struct mi_builder *b,
struct anv_address addr,
bool available)
{
mi_store(b, mi_mem64(addr), mi_imm(available));
}
static void
emit_query_pc_availability(struct anv_cmd_buffer *cmd_buffer,
struct anv_address addr,
bool available)
{
cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_POST_SYNC_BIT;
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
genx_batch_emit_pipe_control_write
(&cmd_buffer->batch, cmd_buffer->device->info,
cmd_buffer->state.current_pipeline, WriteImmediateData, addr,
available, 0);
}
/**
* Goes through a series of consecutive query indices in the given pool
* setting all element values to 0 and emitting them as available.
@ -771,11 +794,11 @@ emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
anv_query_address(pool, first_index + i);
for (uint32_t qword = 1; qword < (pool->stride / 8); qword++) {
emit_query_pc_availability(cmd_buffer,
anv_address_add(slot_addr, qword * 8),
false);
emit_query_eop_availability(cmd_buffer,
anv_address_add(slot_addr, qword * 8),
false);
}
emit_query_pc_availability(cmd_buffer, slot_addr, true);
emit_query_eop_availability(cmd_buffer, slot_addr, true);
}
break;
@ -878,9 +901,9 @@ void genX(CmdResetQueryPool)(
case VK_QUERY_TYPE_TIMESTAMP: {
for (uint32_t i = 0; i < queryCount; i++) {
emit_query_pc_availability(cmd_buffer,
anv_query_address(pool, firstQuery + i),
false);
emit_query_eop_availability(cmd_buffer,
anv_query_address(pool, firstQuery + i),
false);
}
/* Add a CS stall here to make sure the PIPE_CONTROL above has