fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-30 20:28:14 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radv: fix bpe for the stencil aspect of depth/stencil copies on transfer queue

Browse source 
Using the bpe of depth+stencil when copying the stencil aspect only
doesn't work.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34143>
(cherry picked from commit 7b15e85b95)
This commit is contained in:
Samuel Pitoiset 2025-03-19 11:39:30 +01:00 • committed by Eric Engestrom
parent b3991dd8fc
commit 7f32247d95
6 changed files with 5 additions and 38 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -3584,7 +3584,7 @@
"description": "radv: fix bpe for the stencil aspect of depth/stencil copies on transfer queue",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null,
"notes": null

8
src/amd/ci/radv-gfx1200-aco-fails.txt
View file

@ -8,11 +8,3 @@ dEQP-VK.api.copy_and_blit.core.resolve_image.whole_copy_before_resolving_transfe
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.2_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.4_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.8_bit,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_optimal,Fail

8
src/amd/ci/radv-navi10-aco-fails.txt
View file

@ -8,11 +8,3 @@ dEQP-VK.api.copy_and_blit.core.resolve_image.whole_copy_before_resolving_transfe
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.2_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.4_bit,Fail
dEQP-VK.api.copy_and_blit.dedicated_allocation.resolve_image.whole_copy_before_resolving_transfer.8_bit,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_optimal,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_general,Fail
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_optimal,Fail

9
src/amd/ci/radv-renoir-aco-skips.txt
View file

@ -1,9 +0,0 @@
# RADV_PERFTEST=transfer_queue hangs
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_optimal

9
src/amd/ci/radv-vega10-aco-skips.txt
View file

@ -1,9 +0,0 @@
# RADV_PERFTEST=transfer_queue hangs
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.general_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d16_unorm_s8_uint_d16_unorm_s8_uint_depth_stencil_aspects.optimal_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.general_optimal
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_general
dEQP-VK.api.copy_and_blit.copy_commands2.image_to_image_transfer_queue.all_formats.depth_stencil.2d_to_2d.d32_sfloat_s8_uint_d32_sfloat_s8_uint_depth_stencil_aspects.optimal_optimal

7
src/amd/vulkan/radv_sdma.c
View file

@ -220,10 +220,11 @@ radv_sdma_get_metadata_config(const struct radv_device *const device, const stru
static uint32_t
radv_sdma_get_tiled_info_dword(const struct radv_device *const device, const struct radv_image *const image,
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource)
const struct radeon_surf *const surf, const VkImageSubresourceLayers subresource,
const VkImageAspectFlags aspect_mask)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint32_t bpe = radv_sdma_get_bpe(image, subresource.aspectMask);
const uint32_t bpe = radv_sdma_get_bpe(image, aspect_mask);
const uint32_t element_size = util_logbase2(bpe);
const uint32_t swizzle_mode = surf->has_stencil ? surf->u.gfx9.zs.stencil_swizzle_mode : surf->u.gfx9.swizzle_mode;
const enum gfx9_resource_type dimension = radv_sdma_surface_resource_type(device, surf);
@ -309,7 +310,7 @@ radv_sdma_get_surf(const struct radv_device *const device, const struct radv_ima
info.va = (va + surf_offset) | surf->tile_swizzle << 8;
info.info_dword = radv_sdma_get_tiled_info_dword(device, image, surf, subresource);
info.info_dword = radv_sdma_get_tiled_info_dword(device, image, surf, subresource, aspect_mask);
info.header_dword = radv_sdma_get_tiled_header_dword(device, image, subresource);
if (pdev->info.sdma_supports_compression &&