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76548 commits

Author SHA1 Message Date
Brian Paul
1cb2108d9b st/mesa: fix frontbuffer glReadPixels regressions
The change "mesa/readpix: Don't clip in _mesa_readpixels()" caused a
few piglit regressions.  The failing tests use glReadPixels to read
from the front color buffer.  The problem is we were trying to read
from a non-existant front color buffer.  The front color buffer is
created on demand in st/mesa.  Since the missing buffer bounds were
effectively 0 x 0 the glReadPixels was totally clipped and returned
early.

The fix involves creating the real front color buffer when we're about
to try reading from it.

Tested with llvmpipe and VMware driver on Linux, Windows.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94253
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94254
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94257
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit 83b589301f)
2016-02-29 10:18:42 +00:00
Oded Gabbay
3610f677db gallium/radeon: Correctly translate colorswaps for big endian
The current code in r600_translate_colorswap uses the swizzle information
to determine which colorswap to use.

This works for BE & LE when the nr_channels is <4, but when nr_channels==4
(e.g. PIPE_FORMAT_A8R8G8B8_UNORM), this method can not be used for both BE
and LE, because the swizzle info is the same for both of them.

As a result, r600g doesn't support 24bit color formats, only 16bit, which
forces the user to choose 16bit color in X server.

This patch fixes this bug by separating the checks for LE and BE and
adapting the swizzle conditions in the BE part of the checks.

Tested on an Evergreen GPU (Cedar GL FirePro 2270) running inside POWER7
Big-Endian Machine.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "11.2" "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit 4b7e219e61)
2016-02-29 10:17:41 +00:00
Marek Olšák
2eaca4a4d8 tgsi/scan: handle holes between VS inputs, assert-fail in other cases
"st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap"
added a vertex shader declaring IN[0] and IN[2], but not IN[1].

Drivers relying on tgsi_shader_info can't handle holes in declarations,
because tgsi_shader_info doesn't track that.

This is just a quick workaround meant for stable that will work for vertex
shaders.

This fixes radeonsi DrawPixels and CopyPixels crashes.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
(cherry picked from commit 190a291b03)
2016-02-29 10:16:13 +00:00
Samuel Pitoiset
96babdd7f3 nvc0/ir: add missing emission of locked load predicate
Like unlocked store on shared memory, locked store can fail and the
second dest which is a predicate must be emitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit 84b9b8f0a3)
2016-02-29 09:59:43 +00:00
Emil Velikov
35b7adb937 Update version to 11.2.0-rc1
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-22 11:42:41 +00:00
Emil Velikov
4cd5e5b48e nouveau: update the Makefile.sources list
Reflect the nv50->g80 change and the new gm107_texture header.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-22 11:40:29 +00:00
Marek Olšák
ff360a52e6 radeonsi: implement binary shaders & shader cache in memory (v2)
v2: handle _mesa_hash_table_insert failure
    other cosmetic changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
1132910e50 gallium/radeon: remove unused radeon_shader_binary_free_* functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
50ac2612d0 radeonsi: make radeon_shader_reloc name string fixed-sized
This will simplify implementations of binary shaders.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
1fe73d55e3 radeonsi: move some struct si_shader members to new struct si_shader_info
This will be part of shader binaries.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
10fa269f4f radeonsi: use smaller types for some si_shader members
in order to decrease the shader size for a shader cache.

v2: add & use SI_MAX_VS_OUTPUTS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
9aaf28da62 radeonsi: enable compiling one variant per shader
Shader stats from VERDE:

Default scheduler:

Totals:
SGPRS: 491272 -> 488672 (-0.53 %)
VGPRS: 289980 -> 311093 (7.28 %)
Code Size: 11091656 -> 11219948 (1.16 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch: 1732608 -> 2246656 (29.67 %) bytes per wave
Max Waves: 78063 -> 77352 (-0.91 %)
Wait states: 0 -> 0 (0.00 %)

Looking at some of the worst regressions, I get:
- The VGPR increase seems to be caused by the fact that if PS has used less
  than 16 VGPRs, now it will always use 16 VGPRs and sometimes even 20.
  However, the wave count remains at 10 if VGPRs <= 24, so no harm there.
- The scratch increase seems to be caused by SGPR spilling.
  The unnecessary SGPR spilling has been an ongoing issue with the compiler
  and it's completely fixable by rematerializing s_loads or reordering
  instructions.

SI scheduler:

Totals:
SGPRS: 374848 -> 374576 (-0.07 %)
VGPRS: 284456 -> 307515 (8.11 %)
Code Size: 11433068 -> 11535452 (0.90 %) bytes
LDS: 97 -> 97 (0.00 %) blocks
Scratch: 509952 -> 522240 (2.41 %) bytes per wave
Max Waves: 79456 -> 78217 (-1.56 %)
Wait states: 0 -> 0 (0.00 %)

VGPRs - same story as before. The SI scheduler doesn't spill SGPRs so much
and generally spills way less than the default scheduler.
(522240 spills vs 2246656 spills)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
754cf171e9 radeonsi: print full shader name before disassembly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
3c98e0b369 radeonsi: compile non-GS middle parts of shaders immediately if enabled
Still disabled.

Only prologs & epilogs are compiled in draw calls, but each variant of those
is compiled only once per process.

VS is always compiled as hw VS.
TES is always compiled as hw VS.

LS and ES stages are always compiled on demand.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
e038f8fd49 radeonsi: rework polygon stippling for PS prolog
Don't use the pstipple module.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
4636d9be4a radeonsi: add PS prolog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:58 +01:00
Marek Olšák
e79bb746ab radeonsi: add PS epilog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
eb10919b83 radeonsi: add TCS epilog
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
e1b21696a3 radeonsi: add VS epilog
It only exports the primitive ID.
Also used by TES when it's compiled as VS.

The VS input location of the primitive ID input is v2.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
70de433dea radeonsi: add VS prolog
This is disabled with use_monolithic_shaders = true.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
19a92886a8 radeonsi: first bits for non-monolithic shaders
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
0303886b10 radeonsi: add code for dumping all shader parts together (v2)
v2: unify some code into si_get_shader_binary_size

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
17eb99d8b9 radeonsi: add code for combining and uploading shaders from 3 shader parts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
9d5bf1a3ef radeonsi: fail compilation if non-GS non-CS shaders have rodata
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
09408764c1 radeonsi: separate 2 pieces of code from create_function
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
292759220c radeonsi: add samplemask parameter to si_export_mrt_color
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
e6aea08b86 radeonsi: add start_instance parameter to get_instance_index_for_fetch
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
dc27456194 radeonsi: separate out shader key bits for prologs & epilogs
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
d995d4830e radeonsi: compute how many input VGPRs fragment shaders have
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
fe1b6ede01 radeonsi: compute how many input SGPRs and VGPRs shaders have
Prologs (shader binaries inserted before the API shader binary) need to
know this, so that they won't change the input registers unintentionally.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Marek Olšák
36202182ac gallium/radeon: add basic code for setting shader return values
LLVMBuildInsertValue will be used on return_value.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-02-21 21:08:57 +01:00
Samuel Pitoiset
3c9ed2015c nvc0: enable compute shaders on Fermi
Kepler compute support is really different than Fermi and it's not
ready yet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:42:32 +01:00
Samuel Pitoiset
14a810e9d0 nv50/ir: add atomics support on shared memory for Fermi
Changes from v3:
 - move the previous OP_SELP change to the previous commit

Changes from v2:
 - make sure the op is OP_SELP when emitting the predicate and add one
   assert
 - use bld.getSSA() for mkOp2()
 - add cross edge between tryLockAndSetBB and joinBB

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:42:32 +01:00
Samuel Pitoiset
e0371e63df nv50/ir: make OP_SELP a compare instruction
This OP_SELP insn will be used to handle compare and swap subops.

Changes from v2:
 - fix logic for GK110+

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:42:29 +01:00
Samuel Pitoiset
0c930557bf nv50/ir: add lock/unlock subops for load/store
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:42:02 +01:00
Samuel Pitoiset
45e85e16f5 nv50/ir: use s[] addr space for shared buffers
Shared memory address space (FILE_MEMORY_SHARED) must be used instead
of global memory when a shared memory area is declared.

Changes from v2:
 - oops, do not remove TGSI_FILE_BUFFER in a switch in
   nv50_ir_from_tgsi.cpp

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:58 +01:00
Samuel Pitoiset
80fc67fba5 nvc0: reduce likelihood of collision for real buffers on Fermi
Reduce likelihood of collision with real buffers by placing the
hole at the top of the 4G area. This fixes some indirect draw+compute
tests with large buffers.

Suggested by Ilia Mirkin.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:53 +01:00
Samuel Pitoiset
807901b639 nvc0: invalidate compute state when switching pipe contexts
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:48 +01:00
Samuel Pitoiset
c6293877f0 nvc0: add support for indirect compute on Fermi
When indirect compute is used, the size of the grid (in blocks) is
stored as three integers inside a buffer. This requires a macro to
set up GRIDDIM_YX and GRIDDIM_Z.

Changes from v2:
 - do not launch the grid if the number of groups for a dimension is 0

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:45 +01:00
Samuel Pitoiset
fa7333a742 nvc0: bind textures/samplers for compute on Fermi
Textures and samplers don't seem to be aliased between COMPUTE and 3D.

Changes from v2:
 - refactor the code to share (almost) the same logic between 3d and
   compute

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:40 +01:00
Samuel Pitoiset
917a5ff6ea nvc0: bind shader buffers for compute on Fermi
This is loosely based on 3D. Shader buffers are bound on c15 (the
driver constbuf) at offset 0x200.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:37 +01:00
Samuel Pitoiset
a9b70a86db nvc0: bind driver constbuf for compute on Fermi
Changes from v3:
 - add new validation state for COMPUTE driver constbuf

Changes from v2:
 - always bind the driver consts even if user params come in via clover

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:32 +01:00
Samuel Pitoiset
527652629d nvc0: add a new validation state for 3D driver constbuf
This will be used to invalidate 3D driver constbuf when using COMPUTE
and vice-versa. This is needed because this CB contains a bunch of
useful information like the addrs of shader buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:29 +01:00
Samuel Pitoiset
57d4251003 nvc0: bind constant buffers for compute on Fermi
Loosely based on 3D.

Changs from v3:
 - invalidate COMPUTE CBs after validating 3D CBs because they are
   aliased

Changes from v2:
 - get rid of the 's' param to nvc0_cb_bo_push() because it doesn't
   matter to upload constbufs for compute using the 3d chan

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:25 +01:00
Samuel Pitoiset
53f92bb7f9 nvc0: allocate an area for compute user constbufs
For compute shaders, we might need to upload uniforms.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-21 10:41:21 +01:00
Samuel Pitoiset
89d25a82e8 nv50: do not advertise about compute shaders
Compute shaders are totally unsupported. This avoids Clover to
report that OpenCL is supported on Tesla because it's a lie.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-20 19:25:12 +01:00
Rhys Kidd
a0f55e91cc docs: Correct typo in LLVMpipe envvar description
Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-02-20 16:15:35 +01:00
Ilia Mirkin
0b10ec1086 st/mesa: force depth mode to GL_RED for sized depth/stencil formats
See commit 9db2098d for the i965 version of this.

This fixes depth in a bunch of dEQP EXT_texture_border_clamp tests. And
probably other ones as well.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2016-02-19 17:37:39 -05:00
Daniel Czarnowski
e6f1a44d14 egl_dri2: set correct error code if swapbuffers fails
A return value of '-1' means that there was error during swap with a
window drawable, in this case we set error as EGL_BAD_NATIVE_WINDOW.

v2: coding style cleanup, better commit message

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-19 18:23:19 +00:00
Dongwon Kim
d1e1563bb6 egl: move Null check to eglGetSyncAttribKHR to prevent Segfault
Null-check on "*value" is currently done in _eglGetSyncAttrib, which is
after eglGetSyncAttribKHR dereferences it.

Move the check a layer up (in the beginning of eglGetSyncAttribKHR) to
avoid segfaults.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
[Emil Velikov: tweak commit message, add stable tag]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-19 18:23:19 +00:00