Commit graph

3375 commits

Author SHA1 Message Date
Daniel Schürmann
0209065229 ac/nir_lower_global_access: require no_unsigned wrap when extracting from 32-bit additions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
2025-10-08 08:53:58 +00:00
Rhys Perry
20af16b4d8 aco: use MTBUF for 64-bit atomic load/store
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A 64-bit atomic load/store should be considered entirely out-of-bounds if
any part of it is out-of-bounds. Since we implemented these as 32-bit vec2
load/store, it would have been possible for the first half to be in-bounds
while the second half is out-of-bounds.

From 9.6.1. Robust Buffer Access of Vulkan 1.4.324 specification:
> Any non-atomic access to a uniform, storage, uniform texel, or storage
> texel buffer wider than 32-bits may be treated as multiple 32-bit
> accesses that are separately bounds checked.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
2025-10-07 17:41:31 +00:00
Timur Kristóf
92ba76710d ac/gpu_info: Add can_chain_ib2 field to ac_gpu_info
GFX6 supports IB2, but not chaining inside IB2.
It only supports chaining in IB1.
See waCpIb2ChainingUnsupported in PAL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
2025-10-07 15:49:01 +00:00
Georg Lehmann
84f26ed117 nir: optimize atomic isub if supported
Foz-DB Navi48:
Totals from 1 (0.00% of 80287) affected shaders:
Instrs: 1641 -> 1637 (-0.24%)
CodeSize: 8472 -> 8456 (-0.19%)
Latency: 19132 -> 19131 (-0.01%)
InvThroughput: 9566 -> 9565 (-0.01%)
Copies: 126 -> 125 (-0.79%)
VALU: 565 -> 563 (-0.35%)
SALU: 439 -> 438 (-0.23%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37702>
2025-10-07 14:07:56 +00:00
Yinjie Yao
f0f95a9ae3 ac/parse_ib: Update vcn ib parser to include missing commands
Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37672>
2025-10-03 14:44:07 +00:00
Daniel Schürmann
0e3bc3d8c0 nir/opt_offsets: call allow_offset_wrap() for try_fold_shared2()
Some checks are pending
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This prevents applying wrapping offsets on GFX6.

Fixes: e1a692f74b ('nir/opt_offsets: allow for unsigned wraps when folding load/store_shared2_amd offsets')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37667>
2025-10-03 07:54:12 +00:00
Daniel Schürmann
93ce29c42e amd: don't allow unsigned wraps for shared memory offsets on GFX6
Fixes: 10266e7b21 ('radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets')
Fixes: dd68825feb ('radeonsi: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37667>
2025-10-03 07:54:12 +00:00
Vitaliy Triang3l Kuzmin
dea20be1b3 ac: Enable HTILE TC Z clear value bug workaround on GFX1013
Some checks are pending
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
2025-10-02 08:29:50 +00:00
Vitaliy Triang3l Kuzmin
4e3a5f60e1 radv,ac: Split has_tc_compat_zrange_bug into Z and ZS, document it
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
2025-10-02 08:29:49 +00:00
Vitaliy Triang3l Kuzmin
5243f292ef radv,ac: GFX10 depth/stencil HTILE mipmap bug info variable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
2025-10-02 08:29:48 +00:00
Timur Kristóf
d3579190d6 ac/nir/ngg: Fix scalarized mesh primitive indices
Some checks are pending
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Take the write_mask into account when storing primitive indices,
otherwise they will end up being stored in the wrong place.

Fixes: 8e24d3426d ("ac/nir/ngg: Refactor MS primitive indices for scalarized IO.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37610>
2025-09-29 08:07:54 +00:00
Timur Kristóf
3dc9c1a91e ac/nir/ngg: Remove dead code for 64-bit mesh shader variables
We already lower all 64-bit I/O to 32-bit before this pass,
and the rest of the code here already asserts that I/O variables
must be 32-bit or smaller.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37610>
2025-09-29 08:07:54 +00:00
Daniel Schürmann
10266e7b21 radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets
Totals from 76 (0.10% of 79839) affected shaders: (Navi48)

Instrs: 237450 -> 237323 (-0.05%); split: -0.05%, +0.00%
CodeSize: 1276732 -> 1275824 (-0.07%); split: -0.07%, +0.00%
Latency: 1123467 -> 1123387 (-0.01%); split: -0.01%, +0.01%
InvThroughput: 364942 -> 364738 (-0.06%); split: -0.06%, +0.00%
Copies: 20654 -> 20636 (-0.09%); split: -0.09%, +0.00%
Branches: 7326 -> 7327 (+0.01%)
PreSGPRs: 5197 -> 5195 (-0.04%)
PreVGPRs: 3395 -> 3396 (+0.03%)
VALU: 96134 -> 96034 (-0.10%)
SALU: 48059 -> 48041 (-0.04%); split: -0.04%, +0.00%
VOPD: 10 -> 8 (-20.00%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
2025-09-24 14:28:24 +00:00
Rhys Perry
92a2ab8b64 ac/nir: fix progress reporting in ac_nir_lower_tex
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
2025-09-24 08:20:27 +00:00
Georg Lehmann
714a149396 nir: remove unsigned upper bound config
All config information is now either in nir->info or nir->options.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
2025-09-16 09:24:04 +00:00
Qiang Yu
310cfda034 ac/surface: add ac_compute_surface_modifier
Used by radeonsi to export existing texture modifier.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
2025-09-15 09:39:19 +00:00
Qiang Yu
98cd68ec05 ac/surface: add radeonsi exported modifiers to supported list
radeonsi will export texture with these modifiers.

piglit tests:
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export-tex
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-tex-modifier

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
2025-09-15 09:39:19 +00:00
Qiang Yu
1b0ec56c40 ac/surface: refine supported modifier list for multi block size
Reference KMD convert_tiling_flags_to_modifier(). And we are
going to add 4K block size.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
2025-09-15 09:39:19 +00:00
Georg Lehmann
76a502d75a ac/nir: set subgroup size for gs copy shader
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37294>
2025-09-14 13:21:21 +00:00
David Rosca
070c3d2b89 ac/vcn: Add RADEON_VCN_IB_COMMON_OP_RESOLVEINPUTPARAMLAYOUT
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37156>
2025-09-08 10:52:05 +00:00
Georg Lehmann
83326af899 nir/builder: add nir_inverse_ballot_imm
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
2025-09-04 14:03:56 +00:00
Georg Lehmann
ef8c364d3d nir: make inverse_ballot 1bit only
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37178>
2025-09-04 14:03:56 +00:00
David Rosca
2667db1114 radeonsi/vcn: Correctly set chroma location with EFC
EFC supports horizontal left and vertical top/center.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36977>
2025-09-01 10:30:38 +00:00
Marek Olšák
9e16ed7a13 ac/nir: switch nir_load_smem_amd uses to ac_nir_load_smem wrapper
Some checks are pending
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ac_nir_load_smem will use load_global_amd

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37101>
2025-08-30 15:04:32 -04:00
Antonio Ospite
18ef7b82c6 radv: don't include amdgpu.h directly
Don't include amdgpu.h directly in AMDGPU/RADV code, the only libdrm
pieces that are needed are handled in src/amd/common/ac_linux_drm.h
which already includes amdgpu.h

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36932>
2025-08-28 18:08:20 +00:00
Georg Lehmann
13a9f27432 ac/nir: do not assume mesh cull flag is 1bit
It will no longer be 1bit after a nir/lower_io bug is fixed.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36966>
2025-08-27 08:46:33 +00:00
Arseny Kapoulkine
bb3727ce5a ac/rgp: Warn when RGP capture can't be saved without libelf
Without this, mesa build on some distros may silently produce a version
of radv that silently refuses to save RGP traces

Signed-off-by: Arseny Kapoulkine <arseny.kapoulkine@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36960>
2025-08-26 00:42:16 +00:00
Konstantin Seurer
9df7b48d2f nir: Use nir_def_as_* in more places
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36746>
2025-08-24 14:03:09 +00:00
Yonggang Luo
9034a19aba radv: Fixes warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type';
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): error C2220: the following warning is treated as an error
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1040): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings
../src/amd/vulkan/layers/radv_sqtt_layer.c(1052): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1052): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings
../src/amd/vulkan/layers/radv_sqtt_layer.c(1059): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/layers/radv_sqtt_layer.c(1059): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings

../src/amd/vulkan/radv_dgc.c(2155): error C2220: the following warning is treated as an error
../src/amd/vulkan/radv_dgc.c(2155): warning C5287: operands are different enum types 'rgp_sqtt_marker_event_type' and 'rgp_sqtt_marker_general_api_type'; use an explicit cast to silence this warning
../src/amd/vulkan/radv_dgc.c(2155): note: to simplify migration, consider the temporary use of /Wv:18 flag with the version of the compiler with which you used to build without warnings

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36862>
2025-08-20 11:39:19 +00:00
Yonggang Luo
652e0d8ccf amdcommon: Use { 0 } initialize struct for .c files
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36862>
2025-08-20 11:39:19 +00:00
David Rosca
231d877cc8 ac/vcn_dec: Add av1_intrabc_workaround
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36725>
2025-08-20 09:51:32 +00:00
Daniel Schürmann
52cd5f7e69 ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions
Totals from 1400 (1.75% of 79839) affected shaders: (Navi48)

MaxWaves: 38313 -> 38317 (+0.01%); split: +0.06%, -0.05%
Instrs: 1162521 -> 1199627 (+3.19%); split: -0.01%, +3.20%
CodeSize: 5874288 -> 6146832 (+4.64%); split: -0.01%, +4.65%
VGPRs: 79948 -> 79984 (+0.05%); split: -0.12%, +0.17%
Latency: 3703961 -> 3741457 (+1.01%); split: -0.02%, +1.04%
InvThroughput: 589594 -> 590597 (+0.17%); split: -0.06%, +0.23%
VClause: 22561 -> 22564 (+0.01%)
SClause: 19615 -> 19611 (-0.02%); split: -0.03%, +0.01%
Copies: 70721 -> 71678 (+1.35%); split: -0.25%, +1.60%
PreVGPRs: 61068 -> 61101 (+0.05%); split: -0.00%, +0.06%
VALU: 651754 -> 651785 (+0.00%); split: -0.07%, +0.07%
SALU: 141953 -> 141955 (+0.00%)
VOPD: 489 -> 485 (-0.82%); split: +0.41%, -1.23%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
2025-08-19 14:28:14 +00:00
Daniel Schürmann
63f7a03dd1 ac/nir: use HW-requirements on alignment for vectorizing LDS
Totals from 663 (0.83% of 79839) affected shaders: (Navi48)

MaxWaves: 16758 -> 16752 (-0.04%)
Instrs: 748063 -> 750213 (+0.29%); split: -0.08%, +0.37%
CodeSize: 3864912 -> 3874984 (+0.26%); split: -0.11%, +0.37%
VGPRs: 40640 -> 40604 (-0.09%); split: -0.30%, +0.21%
Latency: 6977888 -> 6980523 (+0.04%); split: -0.05%, +0.09%
InvThroughput: 1176313 -> 1174557 (-0.15%); split: -0.23%, +0.08%
VClause: 13852 -> 13843 (-0.06%); split: -0.10%, +0.04%
SClause: 13221 -> 13219 (-0.02%)
Copies: 44814 -> 44760 (-0.12%); split: -0.41%, +0.29%
PreSGPRs: 29276 -> 29285 (+0.03%)
PreVGPRs: 30835 -> 30861 (+0.08%); split: -0.11%, +0.19%
VALU: 423942 -> 423782 (-0.04%); split: -0.21%, +0.17%
SALU: 81271 -> 81188 (-0.10%); split: -0.19%, +0.09%
VOPD: 243 -> 238 (-2.06%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36133>
2025-08-19 14:28:14 +00:00
Georg Lehmann
9ed94371f7 amd: stop using custom gl_access_qualifier for access type
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36764>
2025-08-15 08:26:10 +00:00
Georg Lehmann
f17cb6b714 amd: replace ACCESS_TYPE_SMEM with ACCESS_SMEM_AMD
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36764>
2025-08-15 08:26:10 +00:00
Yinjie Yao
4cb6094f2e ac,radeonsi/vcn: Use correct swizzle_mode for vcn4
On VCN4 SWIZZLE_MODE_8x8_1D_THIN_12_24BPP use different value
than previous VCN generations

Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36775>
2025-08-14 17:24:40 +00:00
Samuel Pitoiset
a2d996b70c ac/descriptors: add a function to create a descriptor for HiZ surfaces
HiZ is a separate image using standard image layout and tiling.
No need to support HiS which isn't available in any production chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
2025-08-12 13:48:09 +00:00
Samuel Pitoiset
b2ea120732 ac,radv,radeonsi: fix programming PA_SU_PRIM_FILTER_CNTL on GFX12
GFX12 seems to behave slightly differently. Setting these bits to TRUE
causes zero-area triangles to not pass the primitive clipping stage.
So, the actual number of primitives output by the primitive clipping
stage was wrong.

After digging a lot, it seems PAL doesn't set these bits either on
GFX12.

CC: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36670>
2025-08-12 07:06:36 +00:00
Marek Olšák
d93156c2a2 ac: merge AC_ARG_INT & AC_ARG_FLOAT into single AC_ARG_VALUE
nothing uses the type anymore

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
2025-08-11 15:32:30 -04:00
Marek Olšák
bb8d2e55d1 ac/llvm: make AC_ARG_FLOAT equal to AC_ARG_INT
Nothing cares about the type anymore.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
2025-08-11 15:32:29 -04:00
Marek Olšák
54fe9aa664 ac: simplify AC_ARG_CONST_*PTR enums
The pointer type doesn't matter anymore.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36696>
2025-08-11 15:32:23 -04:00
David Rosca
d1165984e9 ac/vcn_dec: Add RDECODE_IT_SCALING_TABLE_SIZE
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36645>
2025-08-08 09:22:54 +00:00
Marek Olšák
900e56fc44 ac/nir: clarify the behavior of ac_nir_lower_ngg_options::can_cull
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
2025-08-07 18:12:53 +00:00
Marek Olšák
9244618e5f ac/nir/meta: allow compute blits with R5G6B5 & R5G5B5A1 formats on GFX9+
v2: add a workaround for incorrect hw rounding

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36578>
2025-08-07 18:12:52 +00:00
Yonggang Luo
d83234c8f3 radv: Move the amdgpu.h defines for Win32 to ac_linux_drm.h
This is for fixes compiling with MINGW/GCC

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36598>
2025-08-07 07:47:42 +00:00
jglrxavpok
b987ec42ac radv: Avoid calls to strlen when parsing umr output to speed up hang progressing
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36451>
2025-08-07 06:44:41 +00:00
Hans-Kristian Arntzen
d7b17d4d9c ac/nir: Avoid 0/0 when computing texel buffer size on Polaris.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13349
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36571>
2025-08-06 10:37:50 +00:00
Samuel Pitoiset
1f490c836b ac/gpu_info,radv: use the maximum virtual address from the kernel
Instead of hardcoding it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36573>
2025-08-06 07:55:38 +02:00
Qiang Yu
196569b1a4 all: rename gl_shader_stage to mesa_shader_stage
It's not only for GL, change to a generic name.

Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/\bgl_shader_stage\b/mesa_shader_stage/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
2025-08-06 10:28:40 +08:00
Rhys Perry
cec845079e ac/nir/lower_ps: remove barrier for end_invocation_interlock
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
SPIR-V->NIR now inserts this barrier itself.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36513>
2025-08-04 09:30:06 +00:00