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ac/surface: add ac_compute_surface_modifier
Used by radeonsi to export existing texture modifier. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Daniel Stone <daniels@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
This commit is contained in:
Qiang Yu
Marge Bot
parent
98cd68ec05
commit
310cfda034
2 changed files with 146 additions and 0 deletions
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@ -3577,6 +3577,149 @@ static bool gfx12_compute_surface(struct ac_addrlib *addrlib, const struct radeo
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return true;
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}
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static void gfx9_compute_surface_modifier(const struct radeon_info *info,
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struct radeon_surf *surf)
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{
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unsigned block_size_bits = 0;
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switch (surf->u.gfx9.swizzle_mode >> 2) {
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case 0: /* 256B */
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block_size_bits = 8;
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break;
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case 1: /* 4KiB */
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case 5: /* 4KiB _X */
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block_size_bits = 12;
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break;
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case 2: /* 64KiB */
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case 4: /* 64 KiB _T */
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case 6: /* 64 KiB _X */
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block_size_bits = 16;
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break;
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case 7: /* 256 KiB */
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block_size_bits = 18;
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break;
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default:
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UNREACHABLE("invalid tile mode");
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}
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bool is_xor = surf->u.gfx9.swizzle_mode >= 16;
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if (is_xor) {
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if (info->gfx_level == GFX9) {
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unsigned pipe_xor_bits =
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MIN2(G_0098F8_NUM_PIPES(info->gb_addr_config) +
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G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config),
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block_size_bits - 8);
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unsigned bank_xor_bits =
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MIN2(G_0098F8_NUM_BANKS(info->gb_addr_config),
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block_size_bits - 8 - pipe_xor_bits);
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surf->modifier |=
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AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
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AMD_FMT_MOD_SET(BANK_XOR_BITS, bank_xor_bits);
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} else {
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unsigned pipe_xor_bits =
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MIN2(G_0098F8_NUM_PIPES(info->gb_addr_config), block_size_bits - 8);
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unsigned pkrs = 0;
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if (info->gfx_level == GFX10_3) {
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pkrs = MIN2(G_0098F8_NUM_PKRS(info->gb_addr_config),
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block_size_bits - 8 - pipe_xor_bits);
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} else if (info->gfx_level == GFX11) {
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pkrs = G_0098F8_NUM_PKRS(info->gb_addr_config);
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}
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surf->modifier |=
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AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
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AMD_FMT_MOD_SET(PACKERS, pkrs);
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}
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}
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bool is_dcc = !!surf->meta_offset;
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if (is_dcc) {
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surf->modifier |=
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks) |
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AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, surf->u.gfx9.color.dcc.max_compressed_block_size) |
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AMD_FMT_MOD_SET(DCC_PIPE_ALIGN, surf->u.gfx9.color.dcc.pipe_aligned);
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if (info->gfx_level < GFX11)
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surf->modifier |= AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, info->has_dcc_constant_encode);
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if (surf->display_dcc_offset)
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surf->modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1);
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if (info->gfx_level == GFX9 &&
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(surf->u.gfx9.color.dcc.pipe_aligned || surf->display_dcc_offset)) {
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unsigned pipes = G_0098F8_NUM_PIPES(info->gb_addr_config);
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unsigned rb = G_0098F8_NUM_RB_PER_SE(info->gb_addr_config) +
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G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config);
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surf->modifier |= AMD_FMT_MOD_SET(PIPE, pipes) | AMD_FMT_MOD_SET(RB, rb);
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}
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}
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}
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static void gfx12_compute_surface_modifier(struct radeon_surf *surf)
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{
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if (surf->u.gfx9.gfx12_enable_dcc) {
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surf->modifier |=
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AMD_FMT_MOD_SET(DCC, 1) |
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AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, surf->u.gfx9.color.dcc.max_compressed_block_size);
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}
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}
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void ac_compute_surface_modifier(const struct radeon_info *info,
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struct radeon_surf *surf,
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unsigned samples)
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{
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if (info->gfx_level < GFX9 || surf->modifier != DRM_FORMAT_MOD_INVALID)
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return;
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/* skip depth/stencil, PRT, VRS, 1D/3D and MSAA surface */
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if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_PRT | RADEON_SURF_VRS_RATE) ||
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surf->u.gfx9.resource_type != RADEON_RESOURCE_2D ||
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samples > 1)
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return;
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if (surf->is_linear) {
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surf->modifier = DRM_FORMAT_MOD_LINEAR;
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return;
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}
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unsigned version = 0;
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switch (info->gfx_level) {
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case GFX9:
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version = AMD_FMT_MOD_TILE_VER_GFX9;
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break;
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case GFX10:
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version = AMD_FMT_MOD_TILE_VER_GFX10;
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break;
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case GFX10_3:
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version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS;
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break;
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case GFX11:
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case GFX11_5:
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version = AMD_FMT_MOD_TILE_VER_GFX11;
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break;
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case GFX12:
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version = AMD_FMT_MOD_TILE_VER_GFX12;
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break;
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default:
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UNREACHABLE("invalid gfx level");
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}
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surf->modifier =
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AMD_FMT_MOD |
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AMD_FMT_MOD_SET(TILE_VERSION, version) |
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AMD_FMT_MOD_SET(TILE, surf->u.gfx9.swizzle_mode);
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if (info->gfx_level >= GFX12)
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gfx12_compute_surface_modifier(surf);
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else
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gfx9_compute_surface_modifier(info, surf);
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}
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int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info,
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const struct ac_surf_config *config, enum radeon_surf_mode mode,
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struct radeon_surf *surf)
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@ -543,6 +543,9 @@ void ac_surface_print_info(FILE *out, const struct radeon_info *info,
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bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level,
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const struct radeon_surf *surf);
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void ac_compute_surface_modifier(const struct radeon_info *info, struct radeon_surf *surf,
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unsigned samples);
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#ifdef __cplusplus
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}
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#endif
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