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radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets
Totals from 76 (0.10% of 79839) affected shaders: (Navi48) Instrs: 237450 -> 237323 (-0.05%); split: -0.05%, +0.00% CodeSize: 1276732 -> 1275824 (-0.07%); split: -0.07%, +0.00% Latency: 1123467 -> 1123387 (-0.01%); split: -0.01%, +0.01% InvThroughput: 364942 -> 364738 (-0.06%); split: -0.06%, +0.00% Copies: 20654 -> 20636 (-0.09%); split: -0.09%, +0.00% Branches: 7326 -> 7327 (+0.01%) PreSGPRs: 5197 -> 5195 (-0.04%) PreVGPRs: 3395 -> 3396 (+0.03%) VALU: 96134 -> 96034 (-0.10%) SALU: 48059 -> 48041 (-0.04%); split: -0.04%, +0.00% VOPD: 10 -> 8 (-20.00%) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
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3 changed files with 20 additions and 2 deletions
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@ -8,6 +8,7 @@
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#include "ac_nir.h"
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#include "ac_nir_helpers.h"
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#include "nir_builder.h"
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#include "nir_intrinsics.h"
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/* Set NIR options shared by ACO, LLVM, RADV, and radeonsi. */
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void ac_nir_set_options(struct radeon_info *info, bool use_llvm,
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@ -893,3 +894,16 @@ ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_)
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return 32 / phi->def.bit_size;
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}
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bool
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ac_nir_allow_offset_wrap_cb(nir_intrinsic_instr *instr, const void *data)
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{
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switch (instr->intrinsic) {
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case nir_intrinsic_load_shared:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_shared_atomic:
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case nir_intrinsic_shared_atomic_swap:
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return true;
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default: return false;
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}
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}
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@ -441,6 +441,9 @@ ac_nir_store_may_be_subdword(const nir_intrinsic_instr *instr);
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uint8_t
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ac_nir_lower_phis_to_scalar_cb(const nir_instr *instr, const void *_);
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bool
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ac_nir_allow_offset_wrap_cb(nir_intrinsic_instr *instr, const void *data);
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#ifdef __cplusplus
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}
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#endif
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@ -260,8 +260,9 @@ radv_optimize_nir_algebraic(nir_shader *nir, bool opt_offsets, bool opt_mqsad)
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static const nir_opt_offsets_options offset_options = {
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.uniform_max = 0,
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.buffer_max = ~0,
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.shared_max = ~0,
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.shared_atomic_max = ~0,
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.shared_max = UINT16_MAX,
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.shared_atomic_max = UINT16_MAX,
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.allow_offset_wrap_cb = ac_nir_allow_offset_wrap_cb,
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};
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NIR_PASS(_, nir, nir_opt_offsets, &offset_options);
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}
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