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ac/descriptors: add a function to create a descriptor for HiZ surfaces

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HiZ is a separate image using standard image layout and tiling.
No need to support HiS which isn't available in any production chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36739>
This commit is contained in:
Samuel Pitoiset 2025-07-15 09:52:24 +02:00 • committed by Marge Bot
parent c7045e3e63
commit a2d996b70c
2 changed files with 52 additions and 0 deletions
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37
src/amd/common/ac_descriptors.c
View file

@ -1516,3 +1516,40 @@ ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac
if (info->gfx_level < GFX11)
cb->cb_color_info |= S_028C70_DCC_ENABLE(state->dcc_enabled);
}
void
ac_build_gfx12_hiz_descriptor(const struct ac_gfx12_hiz_state *state, uint32_t desc[8])
{
const uint32_t field_last_level = state->num_samples > 1 ? util_logbase2(state->num_samples) : state->last_level;
const uint32_t max_mip = state->num_samples > 1 ? util_logbase2(state->num_samples) : state->num_levels - 1;
const struct radeon_surf *surf = state->surf;
const uint32_t width = surf->u.gfx9.zs.hiz.width_in_tiles;
const uint32_t height = surf->u.gfx9.zs.hiz.height_in_tiles;
const uint64_t va = state->va + surf->u.gfx9.zs.hiz.offset;
desc[0] = (va >> 8) | surf->tile_swizzle;
desc[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
S_00A004_MAX_MIP_GFX12(max_mip) |
S_00A004_FORMAT_GFX12(V_00A004_GFX11_FORMAT_32_UINT) |
S_00A004_BASE_LEVEL(state->num_samples > 1 ? 0 : state->first_level) |
S_00A004_WIDTH_LO(width - 1);
desc[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
S_00A008_HEIGHT(height - 1);
desc[3] = S_00A00C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_00A00C_DST_SEL_Y(V_008F0C_SQ_SEL_0) |
S_00A00C_DST_SEL_Z(V_008F0C_SQ_SEL_0) |
S_00A00C_DST_SEL_W(V_008F0C_SQ_SEL_1) |
S_00A00C_LAST_LEVEL_GFX12(field_last_level) |
S_00A00C_BC_SWIZZLE(V_00A00C_BC_SWIZZLE_XYZW) |
S_00A00C_TYPE(state->type) |
S_00A00C_SW_MODE(surf->u.gfx9.zs.hiz.swizzle_mode);
desc[4] = S_00A010_DEPTH_GFX12(state->last_layer) |
S_00A010_BASE_ARRAY(state->first_layer);
desc[5] = S_00A014_PERF_MOD(4);
desc[6] = S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(1 /*256B*/) |
S_00A018_MAX_COMPRESSED_BLOCK_SIZE(0) |
S_00A018_COMPRESSION_EN(1) |
S_00A018_WRITE_COMPRESS_ENABLE(1);
desc[7] = 0;
}

15
src/amd/common/ac_descriptors.h
View file

@ -304,6 +304,21 @@ void
ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac_mutable_cb_state *state,
struct ac_cb_surface *cb);
struct ac_gfx12_hiz_state {
struct radeon_surf *surf;
uint64_t va;
uint32_t type : 4;
uint32_t num_samples : 5;
uint32_t first_level : 4;
uint32_t last_level : 5;
uint32_t num_levels : 6;
uint32_t first_layer : 13;
uint32_t last_layer : 13;
};
void
ac_build_gfx12_hiz_descriptor(const struct ac_gfx12_hiz_state *state, uint32_t desc[8]);
#ifdef __cplusplus
}
#endif