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all: rename gl_shader_stage to mesa_shader_stage

Browse source 
It's not only for GL, change to a generic name.

Use command:
  find . -type f -not -path '*/.git/*' -exec sed -i 's/\bgl_shader_stage\b/mesa_shader_stage/g' {} +

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
Qiang Yu 2025-08-05 15:54:29 +08:00
parent 4c7244fac5
commit 196569b1a4
292 changed files with 933 additions and 933 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/amd/common/ac_rgp_elf_object_pack.c
View file

@ -48,7 +48,7 @@ char hw_stage_symbol_string[RGP_HW_STAGE_MAX][16] = {
};
static const char *
get_api_stage_string(gl_shader_stage stage)
get_api_stage_string(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -82,7 +82,7 @@ get_hw_stage_symbol(struct rgp_code_object_record *record, unsigned index)
}
static const char *
rt_subtype_from_stage(gl_shader_stage stage)
rt_subtype_from_stage(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_RAYGEN:

2
src/amd/common/ac_rtld.h
View file

@ -68,7 +68,7 @@ typedef bool (*ac_rtld_get_external_symbol_cb)(enum amd_gfx_level gfx_level, voi
struct ac_rtld_open_info {
const struct radeon_info *info;
struct ac_rtld_options options;
gl_shader_stage shader_type;
mesa_shader_stage shader_type;
unsigned wave_size;
unsigned num_parts;

4
src/amd/common/ac_shader_util.c
View file

@ -865,7 +865,7 @@ unsigned ac_compute_cs_workgroup_size(const uint16_t sizes[3], bool variable, un
return sizes[0] * sizes[1] * sizes[2];
}
unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, mesa_shader_stage stage,
unsigned tess_num_patches,
unsigned tess_patch_in_vtx,
unsigned tess_patch_out_vtx)
@ -1352,7 +1352,7 @@ ac_legacy_gs_compute_subgroup_info(enum mesa_prim input_prim, unsigned gs_vertic
* upload depend on the subgroup size.
*/
bool
ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, gl_shader_stage es_stage, bool is_gs,
ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, mesa_shader_stage es_stage, bool is_gs,
enum mesa_prim input_prim, unsigned gs_vertices_out, unsigned gs_invocations,
unsigned max_workgroup_size, unsigned wave_size, unsigned esgs_vertex_stride,
unsigned ngg_lds_vertex_size, unsigned ngg_lds_scratch_size, bool tess_turns_off_ngg,

6
src/amd/common/ac_shader_util.h
View file

@ -282,7 +282,7 @@ void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_cu
unsigned ac_compute_cs_workgroup_size(const uint16_t sizes[3], bool variable, unsigned max);
unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, gl_shader_stage stage,
unsigned ac_compute_lshs_workgroup_size(enum amd_gfx_level gfx_level, mesa_shader_stage stage,
unsigned tess_num_patches,
unsigned tess_patch_in_vtx,
unsigned tess_patch_out_vtx);
@ -304,7 +304,7 @@ void ac_get_scratch_tmpring_size(const struct radeon_info *info, unsigned num_sc
unsigned bytes_per_wave, uint32_t *tmpring_size);
unsigned
ac_ngg_get_scratch_lds_size(gl_shader_stage stage,
ac_ngg_get_scratch_lds_size(mesa_shader_stage stage,
unsigned workgroup_size,
unsigned wave_size,
bool streamout_enabled,
@ -340,7 +340,7 @@ typedef struct {
} ac_ngg_subgroup_info;
bool
ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, gl_shader_stage es_stage, bool is_gs,
ac_ngg_compute_subgroup_info(enum amd_gfx_level gfx_level, mesa_shader_stage es_stage, bool is_gs,
enum mesa_prim input_prim, unsigned gs_vertices_out, unsigned gs_invocations,
unsigned max_workgroup_size, unsigned wave_size, unsigned esgs_vertex_stride,
unsigned ngg_lds_vertex_size, unsigned ngg_lds_scratch_size, bool tess_turns_off_ngg,

8
src/amd/common/nir/ac_nir_lower_ngg.c
View file

@ -907,7 +907,7 @@ clipdist_culling_es_part(nir_builder *b, lower_ngg_nogs_state *s,
}
static unsigned
ngg_nogs_get_culling_pervertex_lds_size(gl_shader_stage stage,
ngg_nogs_get_culling_pervertex_lds_size(mesa_shader_stage stage,
bool uses_instance_id,
bool uses_primitive_id,
unsigned *num_repacked_variables)
@ -1404,7 +1404,7 @@ ngg_nogs_build_streamout(nir_builder *b, lower_ngg_nogs_state *s)
static unsigned
ngg_nogs_get_pervertex_lds_size(lower_ngg_nogs_state *s,
gl_shader_stage stage,
mesa_shader_stage stage,
bool streamout_enabled,
bool export_prim_id,
bool has_user_edgeflags)
@ -1455,7 +1455,7 @@ ngg_nogs_gather_outputs(nir_builder *b, struct exec_list *cf_list, lower_ngg_nog
static unsigned
ac_ngg_nogs_get_pervertex_lds_size(lower_ngg_nogs_state *s,
gl_shader_stage stage,
mesa_shader_stage stage,
bool streamout_enabled,
bool export_prim_id,
bool has_user_edgeflags,
@ -1795,7 +1795,7 @@ ac_nir_lower_ngg_nogs(nir_shader *shader, const ac_nir_lower_ngg_options *option
}
unsigned
ac_ngg_get_scratch_lds_size(gl_shader_stage stage,
ac_ngg_get_scratch_lds_size(mesa_shader_stage stage,
unsigned workgroup_size,
unsigned wave_size,
bool streamout_enabled,

2
src/amd/compiler/aco_shader_info.h
View file

@ -43,7 +43,7 @@ struct aco_vs_prolog_info {
uint32_t misaligned_mask;
uint32_t unaligned_mask;
bool is_ngg;
gl_shader_stage next_stage;
mesa_shader_stage next_stage;
};
struct aco_ps_epilog_info {

2
src/amd/compiler/tests/helpers.cpp
View file

@ -129,7 +129,7 @@ setup_cs(const char* input_spec, enum amd_gfx_level gfx_level, enum radeon_famil
}
bool
setup_nir_cs(enum amd_gfx_level gfx_level, gl_shader_stage stage, enum radeon_family family, const char* subvariant)
setup_nir_cs(enum amd_gfx_level gfx_level, mesa_shader_stage stage, enum radeon_family family, const char* subvariant)
{
if (!set_variant(gfx_level, subvariant))
return false;

2
src/amd/compiler/tests/helpers.h
View file

@ -63,7 +63,7 @@ bool setup_cs(const char* input_spec, enum amd_gfx_level gfx_level,
enum radeon_family family = CHIP_UNKNOWN, const char* subvariant = "",
unsigned wave_size = 64);
bool
setup_nir_cs(enum amd_gfx_level gfx_level, gl_shader_stage stage = MESA_SHADER_COMPUTE,
setup_nir_cs(enum amd_gfx_level gfx_level, mesa_shader_stage stage = MESA_SHADER_COMPUTE,
enum radeon_family family = CHIP_UNKNOWN, const char* subvariant = "");
void finish_program(aco::Program* program, bool endpgm = true, bool dominance = false);

2
src/amd/llvm/ac_llvm_build.c
View file

@ -386,7 +386,7 @@ LLVMValueRef ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type, unsigne
return phi;
}
void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage)
void ac_build_s_barrier(struct ac_llvm_context *ctx, mesa_shader_stage stage)
{
/* GFX6 only: s_barrier isn’t needed in TCS because an entire patch always fits into
* a single wave due to a bug workaround disallowing multi-wave HS workgroups.

2
src/amd/llvm/ac_llvm_build.h
View file

@ -176,7 +176,7 @@ void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned bufsize);
LLVMValueRef ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type, unsigned count_incoming,
LLVMValueRef *values, LLVMBasicBlockRef *blocks);
void ac_build_s_barrier(struct ac_llvm_context *ctx, gl_shader_stage stage);
void ac_build_s_barrier(struct ac_llvm_context *ctx, mesa_shader_stage stage);
void ac_build_optimization_barrier(struct ac_llvm_context *ctx, LLVMValueRef *pgpr, bool sgpr);
LLVMValueRef ac_build_shader_clock(struct ac_llvm_context *ctx, mesa_scope scope);

2
src/amd/llvm/ac_nir_to_llvm.c
View file

@ -24,7 +24,7 @@ struct ac_nir_context {
struct ac_shader_abi *abi;
const struct ac_shader_args *args;
gl_shader_stage stage;
mesa_shader_stage stage;
shader_info *info;
LLVMValueRef *ssa_defs;

2
src/amd/vulkan/layers/radv_sqtt_layer.c
View file

@ -43,7 +43,7 @@ radv_sqtt_emit_relocated_shaders(struct radv_cmd_buffer *cmd_buffer, struct radv
}
static uint64_t
radv_sqtt_shader_get_va_reloc(struct radv_pipeline *pipeline, gl_shader_stage stage)
radv_sqtt_shader_get_va_reloc(struct radv_pipeline *pipeline, mesa_shader_stage stage)
{
if (pipeline->type == RADV_PIPELINE_GRAPHICS) {
struct radv_graphics_pipeline *graphics_pipeline = radv_pipeline_to_graphics(pipeline);

2
src/amd/vulkan/nir/radv_meta_nir.c
View file

@ -16,7 +16,7 @@
#include "radv_physical_device.h"
nir_builder PRINTFLIKE(3, 4)
radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...)
radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...)
{
const struct radv_physical_device *pdev = radv_device_physical(dev);
nir_builder b = nir_builder_init_simple_shader(stage, NULL, NULL);

2
src/amd/vulkan/nir/radv_meta_nir.h
View file

@ -22,7 +22,7 @@ struct radv_device;
struct radeon_surf;
nir_builder PRINTFLIKE(3, 4)
radv_meta_nir_init_shader(struct radv_device *dev, gl_shader_stage stage, const char *name, ...);
radv_meta_nir_init_shader(struct radv_device *dev, mesa_shader_stage stage, const char *name, ...);
nir_shader *radv_meta_nir_build_vs_generate_vertices(struct radv_device *dev);
nir_shader *radv_meta_nir_build_fs_noop(struct radv_device *dev);

2
src/amd/vulkan/nir/radv_nir_lower_abi.c
View file

@ -63,7 +63,7 @@ static bool
lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
{
lower_abi_state *s = (lower_abi_state *)state;
gl_shader_stage stage = b->shader->info.stage;
mesa_shader_stage stage = b->shader->info.stage;
b->cursor = nir_before_instr(&intrin->instr);

2
src/amd/vulkan/nir/radv_nir_rt_shader.c
View file

@ -1917,7 +1917,7 @@ lower_rt_instructions_monolithic(nir_shader *shader, struct radv_device *device,
static nir_def *
select_next_shader(nir_builder *b, nir_def *shader_addr, unsigned wave_size)
{
gl_shader_stage stage = b->shader->info.stage;
mesa_shader_stage stage = b->shader->info.stage;
nir_def *prio = nir_iand_imm(b, shader_addr, radv_rt_priority_mask);
nir_def *ballot = nir_ballot(b, 1, wave_size, nir_imm_bool(b, true));
nir_def *ballot_traversal = nir_ballot(b, 1, wave_size, nir_ieq_imm(b, prio, radv_rt_priority_traversal));

10
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -2178,7 +2178,7 @@ radv_emit_hw_ngg(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader *e
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const uint64_t va = radv_shader_get_va(shader);
gl_shader_stage es_type;
mesa_shader_stage es_type;
const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
if (shader->info.stage == MESA_SHADER_GEOMETRY) {
@ -7702,7 +7702,7 @@ radv_bind_rt_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *rt_p
/* This function binds/unbinds a shader to the cmdbuffer state. */
static void
radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, gl_shader_stage stage)
radv_bind_shader(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader, mesa_shader_stage stage)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
@ -10860,7 +10860,7 @@ radv_emit_streamout_enable_state(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_ENABLE;
}
static gl_shader_stage
static mesa_shader_stage
radv_cmdbuf_get_last_vgt_api_stage(const struct radv_cmd_buffer *cmd_buffer)
{
if (cmd_buffer->state.active_stages & VK_SHADER_STAGE_MESH_BIT_EXT)
@ -11504,7 +11504,7 @@ radv_bind_graphics_shaders(struct radv_cmd_buffer *cmd_buffer)
}
/* Determine the last VGT shader. */
const gl_shader_stage last_vgt_api_stage = radv_cmdbuf_get_last_vgt_api_stage(cmd_buffer);
const mesa_shader_stage last_vgt_api_stage = radv_cmdbuf_get_last_vgt_api_stage(cmd_buffer);
assume(last_vgt_api_stage != MESA_SHADER_NONE);
if (pdev->info.has_vgt_flush_ngg_legacy_bug &&
@ -14483,7 +14483,7 @@ radv_CmdBindShadersEXT(VkCommandBuffer commandBuffer, uint32_t stageCount, const
VkShaderStageFlagBits bound_stages = 0;
for (uint32_t i = 0; i < stageCount; i++) {
const gl_shader_stage stage = vk_to_mesa_shader_stage(pStages[i]);
const mesa_shader_stage stage = vk_to_mesa_shader_stage(pStages[i]);
if (!pShaders) {
cmd_buffer->state.shader_objs[stage] = NULL;

2
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -698,7 +698,7 @@ radv_get_push_constants_state(const struct radv_cmd_buffer *cmd_buffer, VkPipeli
}
static inline bool
radv_cmdbuf_has_stage(const struct radv_cmd_buffer *cmd_buffer, gl_shader_stage stage)
radv_cmdbuf_has_stage(const struct radv_cmd_buffer *cmd_buffer, mesa_shader_stage stage)
{
return !!(cmd_buffer->state.active_stages & mesa_to_vk_shader_stage(stage));
}

4
src/amd/vulkan/radv_debug.c
View file

@ -439,7 +439,7 @@ radv_add_split_disasm(const char *disasm, uint64_t start_addr, unsigned *num, st
}
static void
radv_dump_annotated_shader(const struct radv_shader *shader, gl_shader_stage stage, struct ac_wave_info *waves,
radv_dump_annotated_shader(const struct radv_shader *shader, mesa_shader_stage stage, struct ac_wave_info *waves,
unsigned num_waves, FILE *f)
{
uint64_t start_addr, end_addr;
@ -520,7 +520,7 @@ radv_dump_spirv(const struct radv_shader *shader, const char *sha1, const char *
static void
radv_dump_shader(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader,
gl_shader_stage stage, const char *dump_dir, FILE *f)
mesa_shader_stage stage, const char *dump_dir, FILE *f)
{
const struct radv_physical_device *pdev = radv_device_physical(device);

16
src/amd/vulkan/radv_dgc.c
View file

@ -132,7 +132,7 @@ radv_dgc_use_preamble(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo)
struct radv_shader *
radv_dgc_get_shader(const VkGeneratedCommandsPipelineInfoEXT *pipeline_info,
const VkGeneratedCommandsShaderInfoEXT *eso_info, gl_shader_stage stage)
const VkGeneratedCommandsShaderInfoEXT *eso_info, mesa_shader_stage stage)
{
if (pipeline_info) {
VK_FROM_HANDLE(radv_pipeline, pipeline, pipeline_info->pipeline);
@ -411,7 +411,7 @@ radv_get_sequence_size(const struct radv_indirect_command_layout *layout, const
for (unsigned i = 0; i < eso_info->shaderCount; ++i) {
VK_FROM_HANDLE(radv_shader_object, shader_object, eso_info->pShaders[i]);
struct radv_shader *shader = shader_object->shader;
gl_shader_stage stage = shader->info.stage;
mesa_shader_stage stage = shader->info.stage;
shaders[stage] = shader;
}
@ -1576,7 +1576,7 @@ dgc_get_push_constant_stages(struct dgc_cmdbuf *cs)
}
static nir_def *
dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage)
dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage)
{
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
@ -1593,7 +1593,7 @@ dgc_get_upload_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stag
}
static nir_def *
dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage)
dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage)
{
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
@ -1610,7 +1610,7 @@ dgc_get_inline_sgpr(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stag
}
static nir_def *
dgc_get_inline_mask(struct dgc_cmdbuf *cs, nir_def *param_offset, gl_shader_stage stage)
dgc_get_inline_mask(struct dgc_cmdbuf *cs, nir_def *param_offset, mesa_shader_stage stage)
{
const struct radv_indirect_command_layout *layout = cs->layout;
nir_builder *b = cs->b;
@ -1693,7 +1693,7 @@ dgc_alloc_push_constant(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *se
static void
dgc_emit_push_constant_for_stage(struct dgc_cmdbuf *cs, nir_def *stream_addr, nir_def *sequence_id,
const struct dgc_pc_params *params, gl_shader_stage stage)
const struct dgc_pc_params *params, mesa_shader_stage stage)
{
const struct radv_indirect_command_layout *layout = cs->layout;
VK_FROM_HANDLE(radv_pipeline_layout, pipeline_layout, layout->vk.layout);
@ -3047,7 +3047,7 @@ radv_prepare_dgc_graphics(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedC
const VkGeneratedCommandsShaderInfoEXT *eso_info =
vk_find_struct_const(pGeneratedCommandsInfo->pNext, GENERATED_COMMANDS_SHADER_INFO_EXT);
const gl_shader_stage first_stage =
const mesa_shader_stage first_stage =
(layout->vk.dgc_info & BITFIELD_BIT(MESA_VK_DGC_DRAW_MESH)) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX;
struct radv_shader *first_shader = radv_dgc_get_shader(pipeline_info, eso_info, first_stage);
@ -3206,7 +3206,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
for (unsigned i = 0; i < eso_info->shaderCount; ++i) {
VK_FROM_HANDLE(radv_shader_object, shader_object, eso_info->pShaders[i]);
struct radv_shader *shader = shader_object->shader;
gl_shader_stage stage = shader->info.stage;
mesa_shader_stage stage = shader->info.stage;
shaders[stage] = shader;
}

2
src/amd/vulkan/radv_dgc.h
View file

@ -65,6 +65,6 @@ bool radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer,
const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
struct radv_shader *radv_dgc_get_shader(const VkGeneratedCommandsPipelineInfoEXT *pipeline_info,
const VkGeneratedCommandsShaderInfoEXT *eso_info, gl_shader_stage stage);
const VkGeneratedCommandsShaderInfoEXT *eso_info, mesa_shader_stage stage);
#endif /* RADV_DGC_H */

8
src/amd/vulkan/radv_nir_to_llvm.c
View file

@ -31,7 +31,7 @@ struct radv_shader_context {
const struct radv_shader_info *shader_info;
const struct radv_shader_args *args;
gl_shader_stage stage;
mesa_shader_stage stage;
unsigned max_workgroup_size;
LLVMContextRef context;
@ -63,7 +63,7 @@ create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module, LLVMBuil
}
static enum ac_llvm_calling_convention
get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
get_llvm_calling_convention(LLVMValueRef func, mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -89,13 +89,13 @@ get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
/* Returns whether the stage is a stage that can be directly before the GS */
static bool
is_pre_gs_stage(gl_shader_stage stage)
is_pre_gs_stage(mesa_shader_stage stage)
{
return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
}
static void
create_function(struct radv_shader_context *ctx, gl_shader_stage stage, bool has_previous_stage)
create_function(struct radv_shader_context *ctx, mesa_shader_stage stage, bool has_previous_stage)
{
if (ctx->ac.gfx_level >= GFX10) {
if (is_pre_gs_stage(stage) && ctx->shader_info->is_ngg) {

2
src/amd/vulkan/radv_physical_device.h
View file

@ -256,7 +256,7 @@ vk_queue_to_radv(const struct radv_physical_device *pdev, int queue_family_index
* specific shader stage (developers only).
*/
static inline bool
radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED gl_shader_stage stage)
radv_use_llvm_for_stage(const struct radv_physical_device *pdev, UNUSED mesa_shader_stage stage)
{
return pdev->use_llvm;
}

12
src/amd/vulkan/radv_pipeline.c
View file

@ -137,7 +137,7 @@ radv_pipeline_get_shader_key(const struct radv_device *device, const VkPipelineS
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
struct vk_pipeline_robustness_state rs;
struct radv_shader_stage_key key = {0};
@ -225,7 +225,7 @@ radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPipeline
}
void
radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, gl_shader_stage stage,
radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, mesa_shader_stage stage,
struct radv_shader_layout *layout)
{
layout->num_sets = pipeline_layout->num_sets;
@ -740,7 +740,7 @@ radv_get_executable_count(struct radv_pipeline *pipeline)
}
static struct radv_shader *
radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
radv_get_shader_from_executable_index(struct radv_pipeline *pipeline, int index, mesa_shader_stage *stage)
{
if (pipeline->type == RADV_PIPELINE_RAY_TRACING) {
struct radv_ray_tracing_pipeline *rt_pipeline = radv_pipeline_to_ray_tracing(pipeline);
@ -794,7 +794,7 @@ radv_GetPipelineExecutablePropertiesKHR(VkDevice _device, const VkPipelineInfoKH
if (!props)
continue;
gl_shader_stage stage;
mesa_shader_stage stage;
struct radv_shader *shader = radv_get_shader_from_executable_index(pipeline, executable_idx, &stage);
props->stages = mesa_to_vk_shader_stage(stage);
@ -884,7 +884,7 @@ radv_GetPipelineExecutableStatisticsKHR(VkDevice _device, const VkPipelineExecut
{
VK_FROM_HANDLE(radv_device, device, _device);
VK_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
gl_shader_stage stage;
mesa_shader_stage stage;
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
@ -1070,7 +1070,7 @@ radv_GetPipelineExecutableInternalRepresentationsKHR(
VK_FROM_HANDLE(radv_device, device, _device);
VK_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
const struct radv_physical_device *pdev = radv_device_physical(device);
gl_shader_stage stage;
mesa_shader_stage stage;
struct radv_shader *shader =
radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);

2
src/amd/vulkan/radv_pipeline.h
View file

@ -91,7 +91,7 @@ void radv_pipeline_stage_init(VkPipelineCreateFlags2 pipeline_flags, const VkPip
const struct radv_pipeline_layout *layout, const struct radv_shader_stage_key *stage_key,
struct radv_shader_stage *out_stage);
void radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, gl_shader_stage stage,
void radv_shader_layout_init(const struct radv_pipeline_layout *pipeline_layout, mesa_shader_stage stage,
struct radv_shader_layout *layout);
void radv_postprocess_nir(struct radv_device *device, const struct radv_graphics_state_key *gfx_state,

6
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -365,7 +365,7 @@ radv_graphics_pipeline_cache_search(struct radv_device *device, struct vk_pipeli
return false;
for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) {
gl_shader_stage s = pipeline_obj->shaders[i]->info.stage;
mesa_shader_stage s = pipeline_obj->shaders[i]->info.stage;
if (s == MESA_SHADER_VERTEX && i > 0) {
/* The GS copy-shader is a VS placed after all other stages */
assert(i == pipeline_obj->num_shaders - 1 && pipeline->base.shaders[MESA_SHADER_GEOMETRY]);
@ -539,7 +539,7 @@ radv_ray_tracing_pipeline_cache_insert(struct radv_device *device, struct vk_pip
}
nir_shader *
radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache, gl_shader_stage stage,
radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache, mesa_shader_stage stage,
const blake3_hash key)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -704,7 +704,7 @@ radv_pipeline_cache_get_binaries(struct radv_device *device, const VkAllocationC
for (unsigned i = 0; i < pipeline_obj->num_shaders; i++) {
struct radv_shader *shader = pipeline_obj->shaders[i];
gl_shader_stage s = shader->info.stage;
mesa_shader_stage s = shader->info.stage;
if (s == MESA_SHADER_VERTEX && i > 0) {
/* The GS copy-shader is a VS placed after all other stages */

2
src/amd/vulkan/radv_pipeline_cache.h
View file

@ -54,7 +54,7 @@ void radv_ray_tracing_pipeline_cache_insert(struct radv_device *device, struct v
struct radv_ray_tracing_pipeline *pipeline, unsigned num_stages);
nir_shader *radv_pipeline_cache_lookup_nir(struct radv_device *device, struct vk_pipeline_cache *cache,
gl_shader_stage stage, const blake3_hash key);
mesa_shader_stage stage, const blake3_hash key);
void radv_pipeline_cache_insert_nir(struct radv_device *device, struct vk_pipeline_cache *cache, const blake3_hash key,
const nir_shader *nir);

48
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -1014,7 +1014,7 @@ radv_pipeline_init_dynamic_state(const struct radv_device *device, struct radv_g
}
struct radv_shader *
radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage)
radv_get_shader(struct radv_shader *const *shaders, mesa_shader_stage stage)
{
if (stage == MESA_SHADER_VERTEX) {
if (shaders[MESA_SHADER_VERTEX])
@ -1250,7 +1250,7 @@ radv_link_shaders(const struct radv_device *device, struct radv_shader_stage *pr
}
}
static const gl_shader_stage graphics_shader_order[] = {
static const mesa_shader_stage graphics_shader_order[] = {
MESA_SHADER_VERTEX, MESA_SHADER_TESS_CTRL, MESA_SHADER_TESS_EVAL, MESA_SHADER_GEOMETRY,
MESA_SHADER_TASK, MESA_SHADER_MESH,
@ -1431,7 +1431,7 @@ radv_graphics_shaders_link(const struct radv_device *device, const struct radv_g
/* Walk backwards to link */
struct radv_shader_stage *next_stage = NULL;
for (int i = ARRAY_SIZE(graphics_shader_order) - 1; i >= 0; i--) {
gl_shader_stage s = graphics_shader_order[i];
mesa_shader_stage s = graphics_shader_order[i];
if (!stages[s].nir)
continue;
@ -1565,8 +1565,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages)
{
/* Prepare shaders before running nir_opt_varyings. */
for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) {
const gl_shader_stage s = graphics_shader_order[i];
const gl_shader_stage next = stages[s].info.next_stage;
const mesa_shader_stage s = graphics_shader_order[i];
const mesa_shader_stage next = stages[s].info.next_stage;
if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir)
continue;
@ -1595,8 +1595,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages)
/* Optimize varyings from first to last stage. */
for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) {
const gl_shader_stage s = graphics_shader_order[i];
const gl_shader_stage next = stages[s].info.next_stage;
const mesa_shader_stage s = graphics_shader_order[i];
const mesa_shader_stage next = stages[s].info.next_stage;
if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir)
continue;
@ -1623,8 +1623,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages)
/* Optimize varyings from last to first stage. */
for (int i = highest_changed_producer; i >= 0; --i) {
const gl_shader_stage s = graphics_shader_order[i];
const gl_shader_stage next = stages[s].info.next_stage;
const mesa_shader_stage s = graphics_shader_order[i];
const mesa_shader_stage next = stages[s].info.next_stage;
if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir)
continue;
@ -1649,8 +1649,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages)
/* Run optimizations and fixups after linking. */
for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) {
const gl_shader_stage s = graphics_shader_order[i];
const gl_shader_stage next = stages[s].info.next_stage;
const mesa_shader_stage s = graphics_shader_order[i];
const mesa_shader_stage next = stages[s].info.next_stage;
if (!stages[s].nir)
continue;
@ -1687,8 +1687,8 @@ radv_graphics_shaders_link_varyings(struct radv_shader_stage *stages)
* This needs to be done after all optimizations are done and shader info gathered.
*/
for (int i = 0; i < ARRAY_SIZE(graphics_shader_order); ++i) {
const gl_shader_stage s = graphics_shader_order[i];
const gl_shader_stage next = stages[s].info.next_stage;
const mesa_shader_stage s = graphics_shader_order[i];
const mesa_shader_stage next = stages[s].info.next_stage;
if (!stages[s].nir || next == MESA_SHADER_NONE || !stages[next].nir)
continue;
@ -2027,7 +2027,7 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const VkGr
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->pStages[i];
gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
key.stage_info[s] = radv_pipeline_get_shader_key(device, stage, create_flags, pCreateInfo->pNext);
@ -2150,8 +2150,8 @@ radv_consider_force_vrs(const struct radv_graphics_state_key *gfx_state, const s
return true;
}
static gl_shader_stage
radv_get_next_stage(gl_shader_stage stage, VkShaderStageFlagBits active_nir_stages)
static mesa_shader_stage
radv_get_next_stage(mesa_shader_stage stage, VkShaderStageFlagBits active_nir_stages)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -2233,7 +2233,7 @@ radv_declare_pipeline_args(struct radv_device *device, struct radv_shader_stage
}
if (gfx_level >= GFX9 && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
mesa_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_declare_shader_args(device, gfx_state, &stages[MESA_SHADER_GEOMETRY].info, MESA_SHADER_GEOMETRY, pre_stage,
&stages[MESA_SHADER_GEOMETRY].args);
stages[MESA_SHADER_GEOMETRY].info.user_sgprs_locs = stages[MESA_SHADER_GEOMETRY].args.user_sgprs_locs;
@ -2346,7 +2346,7 @@ radv_graphics_shaders_nir_to_asm(struct radv_device *device, struct vk_pipeline_
((s == MESA_SHADER_GEOMETRY &&
(active_nir_stages & (VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT))) ||
(s == MESA_SHADER_TESS_CTRL && (active_nir_stages & VK_SHADER_STAGE_VERTEX_BIT)))) {
gl_shader_stage pre_stage;
mesa_shader_stage pre_stage;
if (s == MESA_SHADER_GEOMETRY && (active_nir_stages & VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT)) {
pre_stage = MESA_SHADER_TESS_EVAL;
@ -2442,7 +2442,7 @@ radv_pipeline_import_retained_shaders(const struct radv_device *device, struct r
/* Import the stages (SPIR-V only in case of cache hits). */
for (uint32_t i = 0; i < lib->stage_count; i++) {
const VkPipelineShaderStageCreateInfo *sinfo = &lib->stages[i];
gl_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage);
radv_pipeline_stage_init(lib->base.base.create_flags, sinfo, &lib->layout, &lib->stage_keys[s], &stages[s]);
}
@ -2670,7 +2670,7 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
}
radv_foreach_stage (i, active_nir_stages) {
gl_shader_stage next_stage;
mesa_shader_stage next_stage;
if (stages[i].next_stage != MESA_SHADER_NONE) {
next_stage = stages[i].next_stage;
@ -2925,7 +2925,7 @@ radv_generate_graphics_pipeline_state(struct radv_device *device, const VkGraphi
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i];
gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
radv_pipeline_stage_init(create_flags, sinfo, &gfx_state->layout, &gfx_state->key.stage_info[stage],
&gfx_state->stages[stage]);
@ -3032,7 +3032,7 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
gfx_pipeline_lib->stage_count = pCreateInfo->stageCount;
for (unsigned i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
gfx_pipeline_lib->stage_keys[s] = gfx_state->key.stage_info[s];
}
}
@ -3080,7 +3080,7 @@ done:
uint32_t num_feedbacks = 0;
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
creation_feedback->pPipelineStageCreationFeedbacks[num_feedbacks++] = stages[s].feedback;
}
@ -3270,7 +3270,7 @@ radv_pipeline_init_shader_stages_state(const struct radv_device *device, struct
}
}
gl_shader_stage first_stage =
mesa_shader_stage first_stage =
radv_pipeline_has_stage(pipeline, MESA_SHADER_MESH) ? MESA_SHADER_MESH : MESA_SHADER_VERTEX;
const struct radv_shader *shader = radv_get_shader(pipeline->base.shaders, first_stage);

6
src/amd/vulkan/radv_pipeline_graphics.h
View file

@ -112,7 +112,7 @@ struct radv_graphics_pipeline {
uint32_t db_render_control;
/* Last pre-PS API stage */
gl_shader_stage last_vgt_api_stage;
mesa_shader_stage last_vgt_api_stage;
unsigned rast_prim;
@ -173,7 +173,7 @@ struct radv_graphics_lib_pipeline {
RADV_DECL_PIPELINE_DOWNCAST(graphics_lib, RADV_PIPELINE_GRAPHICS_LIB)
static inline bool
radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, gl_shader_stage stage)
radv_pipeline_has_stage(const struct radv_graphics_pipeline *pipeline, mesa_shader_stage stage)
{
return pipeline->base.shaders[stage];
}
@ -589,7 +589,7 @@ struct radv_ia_multi_vgt_param_helpers radv_compute_ia_multi_vgt_param(const str
void radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3]);
struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, gl_shader_stage stage);
struct radv_shader *radv_get_shader(struct radv_shader *const *shaders, mesa_shader_stage stage);
struct radv_ps_epilog_state {
uint8_t color_attachment_count;

6
src/amd/vulkan/radv_pipeline_rt.c
View file

@ -75,7 +75,7 @@ radv_generate_rt_shaders_key(const struct radv_device *device, const VkRayTracin
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->pStages[i];
gl_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(stage->stage);
stage_keys[s] = radv_pipeline_get_shader_key(device, stage, create_flags, pCreateInfo->pNext);
}
@ -303,7 +303,7 @@ radv_init_rt_stage_hashes(const struct radv_device *device, VkPipelineCreateFlag
} else {
for (uint32_t idx = 0; idx < pCreateInfo->stageCount; idx++) {
const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[idx];
gl_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(sinfo->stage);
struct mesa_sha1 ctx;
_mesa_sha1_init(&ctx);
@ -620,7 +620,7 @@ radv_rt_compile_shaders(struct radv_device *device, struct vk_pipeline_cache *ca
int64_t stage_start = os_time_get_nano();
struct radv_shader_stage *stage = &stages[i];
gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->pStages[i].stage);
radv_pipeline_stage_init(pipeline->base.base.create_flags, &pCreateInfo->pStages[i], pipeline_layout,
&stage_keys[s], stage);

2
src/amd/vulkan/radv_pipeline_rt.h
View file

@ -93,7 +93,7 @@ struct radv_ray_tracing_stage_info {
struct radv_ray_tracing_stage {
struct vk_pipeline_cache_object *nir;
struct radv_shader *shader;
gl_shader_stage stage;
mesa_shader_stage stage;
uint32_t stack_size;
struct radv_ray_tracing_stage_info info;

26
src/amd/vulkan/radv_shader.c
View file

@ -49,7 +49,7 @@
#endif
static void
get_nir_options_for_stage(struct radv_physical_device *pdev, gl_shader_stage stage)
get_nir_options_for_stage(struct radv_physical_device *pdev, mesa_shader_stage stage)
{
const struct radv_instance *instance = radv_physical_device_instance(pdev);
nir_shader_compiler_options *options = &pdev->nir_options[stage];
@ -71,7 +71,7 @@ get_nir_options_for_stage(struct radv_physical_device *pdev, gl_shader_stage sta
void
radv_get_nir_options(struct radv_physical_device *pdev)
{
for (gl_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_VULKAN_SHADER_STAGES; stage++)
for (mesa_shader_stage stage = MESA_SHADER_VERTEX; stage < MESA_VULKAN_SHADER_STAGES; stage++)
get_nir_options_for_stage(pdev, stage);
}
@ -111,7 +111,7 @@ is_meta_shader(nir_shader *nir)
}
static uint64_t
radv_dump_flag_for_stage(const gl_shader_stage stage)
radv_dump_flag_for_stage(const mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -1367,7 +1367,7 @@ radv_destroy_shader_upload_queue(struct radv_device *device)
}
static bool
radv_should_use_wgp_mode(const struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info)
radv_should_use_wgp_mode(const struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
enum amd_gfx_level chip = pdev->info.gfx_level;
@ -1963,7 +1963,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
}
const struct radv_shader_info *info = &binary->info;
gl_shader_stage stage = binary->info.stage;
mesa_shader_stage stage = binary->info.stage;
bool scratch_enabled = config->scratch_bytes_per_wave > 0;
const bool trap_enabled = !!device->trap_handler_shader;
/* On GFX12, TRAP_PRESENT doesn't exist for compute shaders and it's enabled by default. */
@ -2031,7 +2031,7 @@ radv_postprocess_binary_config(struct radv_device *device, struct radv_shader_bi
config->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(args->num_user_sgprs >> 5);
}
gl_shader_stage es_stage = MESA_SHADER_NONE;
mesa_shader_stage es_stage = MESA_SHADER_NONE;
if (pdev->info.gfx_level >= GFX9) {
es_stage = stage == MESA_SHADER_GEOMETRY ? info->gs.es_type : stage;
}
@ -2625,7 +2625,7 @@ radv_get_max_waves(const struct radv_device *device, const struct ac_shader_conf
const struct radeon_info *gpu_info = &pdev->info;
const enum amd_gfx_level gfx_level = gpu_info->gfx_level;
const uint8_t wave_size = info->wave_size;
gl_shader_stage stage = info->stage;
mesa_shader_stage stage = info->stage;
unsigned max_simd_waves = gpu_info->max_waves_per_simd;
unsigned lds_per_workgroup = 0;
unsigned waves_per_workgroup = 1;
@ -3074,7 +3074,7 @@ radv_fill_nir_compiler_options(struct radv_nir_compiler_options *options, struct
}
void
radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_shader_stage stage,
radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, mesa_shader_stage stage,
struct radv_shader_stage_key *key)
{
if (rs->storage_buffers == VK_PIPELINE_ROBUSTNESS_BUFFER_BEHAVIOR_ROBUST_BUFFER_ACCESS_2)
@ -3088,7 +3088,7 @@ radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_
}
static struct radv_shader_binary *
shader_compile(struct radv_device *device, struct nir_shader *const *shaders, int shader_count, gl_shader_stage stage,
shader_compile(struct radv_device *device, struct nir_shader *const *shaders, int shader_count, mesa_shader_stage stage,
const struct radv_shader_info *info, const struct radv_shader_args *args,
const struct radv_shader_stage_key *stage_key, struct radv_nir_compiler_options *options)
{
@ -3136,7 +3136,7 @@ radv_shader_nir_to_asm(struct radv_device *device, struct radv_shader_stage *pl_
struct nir_shader *const *shaders, int shader_count,
const struct radv_graphics_state_key *gfx_state, bool keep_shader_info, bool keep_statistic_info)
{
gl_shader_stage stage = shaders[shader_count - 1]->info.stage;
mesa_shader_stage stage = shaders[shader_count - 1]->info.stage;
struct radv_shader_info *info = &pl_stage->info;
bool dump_shader = false;
@ -3177,7 +3177,7 @@ radv_create_trap_handler_shader(struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_instance *instance = radv_physical_device_instance(pdev);
gl_shader_stage stage = MESA_SHADER_COMPUTE;
mesa_shader_stage stage = MESA_SHADER_COMPUTE;
struct radv_shader_stage_key stage_key = {0};
struct radv_shader_info info = {0};
struct radv_nir_compiler_options options = {0};
@ -3490,7 +3490,7 @@ radv_find_shader(struct radv_device *device, uint64_t pc)
}
const char *
radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage)
radv_get_shader_name(const struct radv_shader_info *info, mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -3628,7 +3628,7 @@ radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess
VkResult
radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader,
gl_shader_stage stage, FILE *output)
mesa_shader_stage stage, FILE *output)
{
VkPipelineExecutablePropertiesKHR *props = NULL;
uint32_t prop_count = 0;

16
src/amd/vulkan/radv_shader.h
View file

@ -46,7 +46,7 @@ enum {
#define RADV_STAGE_MASK ((1 << MESA_VULKAN_SHADER_STAGES) - 1)
#define radv_foreach_stage(stage, stage_bits) \
for (gl_shader_stage stage, __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
for (mesa_shader_stage stage, __tmp = (mesa_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
stage = ffs(__tmp) - 1, __tmp; __tmp &= ~(1 << (stage)))
enum radv_nggc_settings {
@ -257,8 +257,8 @@ struct radv_shader_layout {
};
struct radv_shader_stage {
gl_shader_stage stage;
gl_shader_stage next_stage;
mesa_shader_stage stage;
mesa_shader_stage next_stage;
struct {
const struct vk_object_base *object;
@ -339,7 +339,7 @@ struct radv_vs_prolog_key {
bool as_ls;
bool is_ngg;
bool wave32;
gl_shader_stage next_stage;
mesa_shader_stage next_stage;
};
enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
@ -608,7 +608,7 @@ unsigned radv_get_max_waves(const struct radv_device *device, const struct ac_sh
unsigned radv_get_max_scratch_waves(const struct radv_device *device, struct radv_shader *shader);
const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage);
const char *radv_get_shader_name(const struct radv_shader_info *info, mesa_shader_stage stage);
unsigned radv_compute_spi_ps_input(const struct radv_physical_device *pdev,
const struct radv_graphics_state_key *gfx_state,
@ -619,7 +619,7 @@ bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir);
bool radv_can_dump_shader_stats(struct radv_device *device, nir_shader *nir);
VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline, struct radv_shader *shader,
gl_shader_stage stage, FILE *output);
mesa_shader_stage stage, FILE *output);
/* Returns true on success and false on failure */
bool radv_shader_reupload(struct radv_device *device, struct radv_shader *shader);
@ -700,7 +700,7 @@ enum radv_rt_priority {
};
static inline enum radv_rt_priority
radv_get_rt_priority(gl_shader_stage stage)
radv_get_rt_priority(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_RAYGEN:
@ -739,7 +739,7 @@ uint32_t radv_get_user_sgpr(const struct radv_shader *shader, int idx);
void radv_precompute_registers_hw_ngg(struct radv_device *device, const struct ac_shader_config *config,
struct radv_shader_info *info);
void radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, gl_shader_stage stage,
void radv_set_stage_key_robustness(const struct vk_pipeline_robustness_state *rs, mesa_shader_stage stage,
struct radv_shader_stage_key *key);
#endif /* RADV_SHADER_H */

8
src/amd/vulkan/radv_shader_args.c
View file

@ -197,7 +197,7 @@ declare_vs_input_vgprs(enum amd_gfx_level gfx_level, const struct radv_shader_in
}
static void
declare_streamout_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args, gl_shader_stage stage)
declare_streamout_sgprs(const struct radv_shader_info *info, struct radv_shader_args *args, mesa_shader_stage stage)
{
int i;
@ -300,7 +300,7 @@ declare_ngg_sgprs(const struct radv_shader_info *info, struct radv_shader_args *
}
static void
radv_init_shader_args(const struct radv_device *device, gl_shader_stage stage, struct radv_shader_args *args)
radv_init_shader_args(const struct radv_device *device, mesa_shader_stage stage, struct radv_shader_args *args)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
memset(args, 0, sizeof(*args));
@ -520,7 +520,7 @@ declare_unmerged_vs_tes_gs_args(const enum amd_gfx_level gfx_level, const struct
static void
declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage,
const struct radv_shader_info *info, mesa_shader_stage stage, mesa_shader_stage previous_stage,
struct radv_shader_args *args, struct user_sgpr_info *user_sgpr_info)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -878,7 +878,7 @@ declare_shader_args(const struct radv_device *device, const struct radv_graphics
void
radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
const struct radv_shader_info *info, gl_shader_stage stage, gl_shader_stage previous_stage,
const struct radv_shader_info *info, mesa_shader_stage stage, mesa_shader_stage previous_stage,
struct radv_shader_args *args)
{
declare_shader_args(device, gfx_state, info, stage, previous_stage, args, NULL);

4
src/amd/vulkan/radv_shader_args.h
View file

@ -135,8 +135,8 @@ struct radv_ps_epilog_key;
struct radv_device;
void radv_declare_shader_args(const struct radv_device *device, const struct radv_graphics_state_key *gfx_state,
const struct radv_shader_info *info, gl_shader_stage stage,
gl_shader_stage previous_stage, struct radv_shader_args *args);
const struct radv_shader_info *info, mesa_shader_stage stage,
mesa_shader_stage previous_stage, struct radv_shader_args *args);
void radv_declare_ps_epilog_args(const struct radv_device *device, const struct radv_ps_epilog_key *key,
struct radv_shader_args *args);

8
src/amd/vulkan/radv_shader_info.c
View file

@ -471,7 +471,7 @@ radv_set_vs_output_param(struct radv_device *device, const struct nir_shader *ni
}
static uint8_t
radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info,
radv_get_wave_size(struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info,
const struct radv_shader_stage_key *stage_key)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
@ -492,7 +492,7 @@ radv_get_wave_size(struct radv_device *device, gl_shader_stage stage, const stru
}
static uint8_t
radv_get_ballot_bit_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info,
radv_get_ballot_bit_size(struct radv_device *device, mesa_shader_stage stage, const struct radv_shader_info *info,
const struct radv_shader_stage_key *stage_key)
{
if (stage_key->subgroup_required_size)
@ -1064,7 +1064,7 @@ radv_is_merged_shader_compiled_separately(const struct radv_device *device, cons
}
void
radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info)
radv_nir_shader_info_init(mesa_shader_stage stage, mesa_shader_stage next_stage, struct radv_shader_info *info)
{
memset(info, 0, sizeof(*info));
@ -1573,7 +1573,7 @@ radv_nir_shader_info_link(struct radv_device *device, const struct radv_graphics
/* Merge shader info for VS+GS or TES+GS. */
if ((stages[MESA_SHADER_VERTEX].nir || stages[MESA_SHADER_TESS_EVAL].nir) && stages[MESA_SHADER_GEOMETRY].nir) {
gl_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
mesa_shader_stage pre_stage = stages[MESA_SHADER_TESS_EVAL].nir ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
radv_nir_shader_info_merge(&stages[pre_stage], &stages[MESA_SHADER_GEOMETRY]);
}

6
src/amd/vulkan/radv_shader_info.h
View file

@ -103,8 +103,8 @@ struct radv_shader_info {
struct radv_vs_output_info outinfo;
unsigned workgroup_size;
bool force_vrs_per_vertex;
gl_shader_stage stage;
gl_shader_stage next_stage;
mesa_shader_stage stage;
mesa_shader_stage next_stage;
enum radv_shader_type type;
uint32_t user_data_0;
bool inputs_linked;
@ -319,7 +319,7 @@ struct radv_shader_info {
} regs;
};
void radv_nir_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info);
void radv_nir_shader_info_init(mesa_shader_stage stage, mesa_shader_stage next_stage, struct radv_shader_info *info);
void radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *nir,
const struct radv_shader_layout *layout, const struct radv_shader_stage_key *stage_key,

6
src/amd/vulkan/radv_shader_object.c
View file

@ -123,7 +123,7 @@ static VkResult
radv_shader_object_init_graphics(struct radv_shader_object *shader_obj, struct radv_device *device,
const VkShaderCreateInfoEXT *pCreateInfo)
{
gl_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage);
mesa_shader_stage stage = vk_to_mesa_shader_stage(pCreateInfo->stage);
struct radv_shader_stage stages[MESA_VULKAN_SHADER_STAGES];
for (unsigned i = 0; i < MESA_VULKAN_SHADER_STAGES; i++) {
@ -440,7 +440,7 @@ radv_shader_object_create_linked(VkDevice _device, uint32_t createInfoCount, con
for (unsigned i = 0; i < createInfoCount; i++) {
const VkShaderCreateInfoEXT *pCreateInfo = &pCreateInfos[i];
gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage);
radv_shader_stage_init(pCreateInfo, &stages[s]);
}
@ -497,7 +497,7 @@ radv_shader_object_create_linked(VkDevice _device, uint32_t createInfoCount, con
for (unsigned i = 0; i < createInfoCount; i++) {
const VkShaderCreateInfoEXT *pCreateInfo = &pCreateInfos[i];
gl_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(pCreateInfo->stage);
struct radv_shader_object *shader_obj;
shader_obj = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*shader_obj), 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);

2
src/amd/vulkan/radv_shader_object.h
View file

@ -16,7 +16,7 @@
struct radv_shader_object {
struct vk_object_base base;
gl_shader_stage stage;
mesa_shader_stage stage;
VkShaderCodeTypeEXT code_type;

2
src/asahi/compiler/agx_compile.c
View file

@ -1322,7 +1322,7 @@ agx_emit_intrinsic(agx_builder *b, nir_intrinsic_instr *instr)
agx_index dst = nir_intrinsic_infos[instr->intrinsic].has_dest
? agx_def_index(&instr->def)
: agx_null();
gl_shader_stage stage = b->shader->stage;
mesa_shader_stage stage = b->shader->stage;
switch (instr->intrinsic) {
case nir_intrinsic_load_barycentric_pixel:

2
src/asahi/compiler/agx_compiler.h
View file

@ -483,7 +483,7 @@ typedef struct agx_block {
typedef struct {
nir_shader *nir;
gl_shader_stage stage;
mesa_shader_stage stage;
bool is_preamble;
unsigned scratch_size_B;

2
src/asahi/vulkan/hk_cmd_buffer.c
View file

@ -337,7 +337,7 @@ hk_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,
void
hk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count,
const gl_shader_stage *stages,
const mesa_shader_stage *stages,
struct vk_shader **const shaders)
{
struct hk_cmd_buffer *cmd = container_of(vk_cmd, struct hk_cmd_buffer, vk);

4
src/asahi/vulkan/hk_cmd_buffer.h
View file

@ -786,11 +786,11 @@ void hk_cmd_invalidate_graphics_state(struct hk_cmd_buffer *cmd);
void hk_cmd_invalidate_compute_state(struct hk_cmd_buffer *cmd);
void hk_cmd_bind_shaders(struct vk_command_buffer *vk_cmd, uint32_t stage_count,
const gl_shader_stage *stages,
const mesa_shader_stage *stages,
struct vk_shader **const shaders);
void hk_cmd_bind_graphics_shader(struct hk_cmd_buffer *cmd,
const gl_shader_stage stage,
const mesa_shader_stage stage,
struct hk_api_shader *shader);
void hk_cmd_bind_compute_shader(struct hk_cmd_buffer *cmd,

4
src/asahi/vulkan/hk_cmd_draw.c
View file

@ -1701,7 +1701,7 @@ hk_launch_tess(struct hk_cmd_buffer *cmd, struct hk_cs *cs,
void
hk_cmd_bind_graphics_shader(struct hk_cmd_buffer *cmd,
const gl_shader_stage stage,
const mesa_shader_stage stage,
struct hk_api_shader *shader)
{
struct hk_device *dev = hk_cmd_buffer_device(cmd);
@ -1946,7 +1946,7 @@ hk_update_fast_linked(struct hk_cmd_buffer *cmd, struct hk_shader *shader,
{
struct hk_device *dev = hk_cmd_buffer_device(cmd);
struct hk_linked_shader *new = hk_get_fast_linked(dev, shader, key);
gl_shader_stage stage = shader->info.stage;
mesa_shader_stage stage = shader->info.stage;
if (cmd->state.gfx.linked[stage] != new) {
cmd->state.gfx.linked[stage] = new;

12
src/asahi/vulkan/hk_shader.c
View file

@ -104,7 +104,7 @@ hk_physical_device_compiler_flags(const struct hk_physical_device *pdev)
}
const nir_shader_compiler_options *
hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage,
hk_get_nir_options(struct vk_physical_device *vk_pdev, mesa_shader_stage stage,
UNUSED const struct vk_pipeline_robustness_state *rs)
{
return &agx_nir_options;
@ -112,7 +112,7 @@ hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage,
static struct spirv_to_nir_options
hk_get_spirv_options(struct vk_physical_device *vk_pdev,
UNUSED gl_shader_stage stage,
UNUSED mesa_shader_stage stage,
const struct vk_pipeline_robustness_state *rs)
{
return (struct spirv_to_nir_options){
@ -971,7 +971,7 @@ DERIVE_HASH_TABLE(hk_fast_link_key_vs);
DERIVE_HASH_TABLE(hk_fast_link_key_fs);
static VkResult
hk_init_link_ht(struct hk_shader *shader, gl_shader_stage sw_stage)
hk_init_link_ht(struct hk_shader *shader, mesa_shader_stage sw_stage)
{
simple_mtx_init(&shader->linked.lock, mtx_plain);
@ -1064,7 +1064,7 @@ hk_compile_nir(struct hk_device *dev, const VkAllocationCallbacks *pAllocator,
nir_shader *nir, VkShaderCreateFlagsEXT shader_flags,
const struct vk_pipeline_robustness_state *rs,
const union hk_key *key, enum hk_feature_key features,
struct hk_shader *shader, gl_shader_stage sw_stage, bool hw,
struct hk_shader *shader, mesa_shader_stage sw_stage, bool hw,
nir_xfb_info *xfb_info, unsigned set_count)
{
unsigned nr_vbos = 0;
@ -1311,7 +1311,7 @@ hk_compile_shader(struct hk_device *dev, struct vk_shader_compile_info *info,
info->set_layouts, features);
}
gl_shader_stage sw_stage = nir->info.stage;
mesa_shader_stage sw_stage = nir->info.stage;
union hk_key key_tmp, *key = NULL;
if (sw_stage == MESA_SHADER_FRAGMENT) {
@ -1640,7 +1640,7 @@ hk_deserialize_api_shader(struct vk_device *vk_dev, struct blob_reader *blob,
{
struct hk_device *dev = container_of(vk_dev, struct hk_device, vk);
gl_shader_stage stage = blob_read_uint8(blob);
mesa_shader_stage stage = blob_read_uint8(blob);
if (blob->overrun)
return vk_error(dev, VK_ERROR_INCOMPATIBLE_SHADER_BINARY_EXT);

6
src/asahi/vulkan/hk_shader.h
View file

@ -105,7 +105,7 @@ struct hk_shader_info {
/* Transform feedback buffer strides */
uint8_t xfb_stride[MAX_XFB_BUFFERS];
gl_shader_stage stage : 8;
mesa_shader_stage stage : 8;
uint8_t clip_distance_array_size;
uint8_t cull_distance_array_size;
uint8_t set_count;
@ -204,7 +204,7 @@ static const char *hk_gs_variant_name[] = {
/* clang-format on */
static inline unsigned
hk_num_variants(gl_shader_stage stage)
hk_num_variants(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -365,7 +365,7 @@ void hk_api_shader_destroy(struct vk_device *vk_dev,
const VkAllocationCallbacks *pAllocator);
const nir_shader_compiler_options *
hk_get_nir_options(struct vk_physical_device *vk_pdev, gl_shader_stage stage,
hk_get_nir_options(struct vk_physical_device *vk_pdev, mesa_shader_stage stage,
UNUSED const struct vk_pipeline_robustness_state *rs);
struct hk_api_shader *hk_meta_shader(struct hk_device *dev,

2
src/broadcom/common/v3d_debug.c
View file

@ -114,7 +114,7 @@ static const struct debug_named_value debug_control[] = {
DEBUG_GET_ONCE_FLAGS_OPTION(v3d_debug, "V3D_DEBUG", debug_control, 0)
bool
v3d_debug_flag_for_shader_stage(gl_shader_stage stage)
v3d_debug_flag_for_shader_stage(mesa_shader_stage stage)
{
uint32_t flags[] = {
[MESA_SHADER_VERTEX] = V3D_DEBUG_VS,

2
src/broadcom/common/v3d_debug.h
View file

@ -93,7 +93,7 @@ extern uint32_t v3d_mesa_debug;
#define dbg_printf(...) fprintf(stderr, __VA_ARGS__)
#endif /* HAVE_ANDROID_PLATFORM */
extern bool v3d_debug_flag_for_shader_stage(gl_shader_stage stage);
extern bool v3d_debug_flag_for_shader_stage(mesa_shader_stage stage);
extern void v3d_process_debug_variable(void);

2
src/broadcom/compiler/v3d_compiler.h
View file

@ -1138,7 +1138,7 @@ uint64_t *v3d_compile(const struct v3d_compiler *compiler,
int program_id, int variant_id,
uint32_t *final_assembly_size);
uint32_t v3d_prog_data_size(gl_shader_stage stage);
uint32_t v3d_prog_data_size(mesa_shader_stage stage);
void v3d_nir_to_vir(struct v3d_compile *c);
void vir_compile_destroy(struct v3d_compile *c);

2
src/broadcom/compiler/vir.c
View file

@ -1828,7 +1828,7 @@ v3d_attempt_compile(struct v3d_compile *c)
}
uint32_t
v3d_prog_data_size(gl_shader_stage stage)
v3d_prog_data_size(mesa_shader_stage stage)
{
static const int prog_data_size[] = {
[MESA_SHADER_VERTEX] = sizeof(struct v3d_vs_prog_data),

14
src/broadcom/vulkan/v3dv_pipeline.c
View file

@ -373,7 +373,7 @@ shader_module_compile_to_nir(struct v3dv_device *device,
const nir_shader_compiler_options *nir_options =
v3dv_pipeline_get_nir_options(&device->devinfo);
gl_shader_stage gl_stage = broadcom_shader_stage_to_gl(stage->stage);
mesa_shader_stage gl_stage = broadcom_shader_stage_to_gl(stage->stage);
const VkPipelineShaderStageCreateInfo stage_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@ -492,7 +492,7 @@ lower_load_push_constant(nir_builder *b, nir_intrinsic_instr *instr,
static struct v3dv_descriptor_map*
pipeline_get_descriptor_map(struct v3dv_pipeline *pipeline,
VkDescriptorType desc_type,
gl_shader_stage gl_stage,
mesa_shader_stage gl_stage,
bool is_sampler)
{
enum broadcom_shader_stage broadcom_stage =
@ -1688,7 +1688,7 @@ pipeline_compile_shader_variant(struct v3dv_pipeline_stage *p_stage,
struct v3dv_pipeline *pipeline = p_stage->pipeline;
struct v3dv_physical_device *physical_device = pipeline->device->pdevice;
const struct v3d_compiler *compiler = physical_device->compiler;
gl_shader_stage gl_stage = broadcom_shader_stage_to_gl(p_stage->stage);
mesa_shader_stage gl_stage = broadcom_shader_stage_to_gl(p_stage->stage);
if (V3D_DBG(NIR) || v3d_debug_flag_for_shader_stage(gl_stage)) {
fprintf(stderr, "Just before v3d_compile: %s prog %d NIR:\n",
@ -2214,7 +2214,7 @@ write_creation_feedback(struct v3dv_pipeline *pipeline,
assert(feedback_stage_count <= stage_count);
for (uint32_t i = 0; i < feedback_stage_count; i++) {
gl_shader_stage s = vk_to_mesa_shader_stage(stages[i].stage);
mesa_shader_stage s = vk_to_mesa_shader_stage(stages[i].stage);
enum broadcom_shader_stage bs = gl_shader_stage_to_broadcom(s);
create_feedback->pPipelineStageCreationFeedbacks[i] =
@ -2439,7 +2439,7 @@ pipeline_compile_graphics(struct v3dv_pipeline *pipeline,
*/
for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
const VkPipelineShaderStageCreateInfo *sinfo = &pCreateInfo->pStages[i];
gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
struct v3dv_pipeline_stage *p_stage =
vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*p_stage), 8,
@ -3187,7 +3187,7 @@ pipeline_compile_compute(struct v3dv_pipeline *pipeline,
struct v3dv_physical_device *physical_device = device->pdevice;
const VkPipelineShaderStageCreateInfo *sinfo = &info->stage;
gl_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
mesa_shader_stage stage = vk_to_mesa_shader_stage(sinfo->stage);
struct v3dv_pipeline_stage *p_stage =
vk_zalloc2(&device->vk.alloc, alloc, sizeof(*p_stage), 8,
@ -3594,7 +3594,7 @@ v3dv_GetPipelineExecutablePropertiesKHR(
util_dynarray_foreach(&pipeline->executables.data,
struct v3dv_pipeline_executable_data, exe) {
vk_outarray_append_typed(VkPipelineExecutablePropertiesKHR, &out, props) {
gl_shader_stage mesa_stage = broadcom_shader_stage_to_gl(exe->stage);
mesa_shader_stage mesa_stage = broadcom_shader_stage_to_gl(exe->stage);
props->stages = mesa_to_vk_shader_stage(mesa_stage);
VK_PRINT_STR(props->name, "%s (%s)",

6
src/broadcom/vulkan/v3dv_private.h
View file

@ -346,7 +346,7 @@ struct v3dv_pipeline_cache_stats {
uint32_t on_disk_hit;
};
/* Equivalent to gl_shader_stage, but including the coordinate shaders
/* Equivalent to mesa_shader_stage, but including the coordinate shaders
*
* FIXME: perhaps move to common
*/
@ -363,7 +363,7 @@ enum broadcom_shader_stage {
/* Assumes that coordinate shaders will be custom-handled by the caller */
static inline enum broadcom_shader_stage
gl_shader_stage_to_broadcom(gl_shader_stage stage)
gl_shader_stage_to_broadcom(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -379,7 +379,7 @@ gl_shader_stage_to_broadcom(gl_shader_stage stage)
}
}
static inline gl_shader_stage
static inline mesa_shader_stage
broadcom_shader_stage_to_gl(enum broadcom_shader_stage stage)
{
switch (stage) {

2
src/compiler/glsl/ast_to_hir.cpp
View file

@ -2787,7 +2787,7 @@ ast_fully_specified_type::glsl_type(const char **name,
* this function will produce undefined results.
*/
static bool
is_varying_var(ir_variable *var, gl_shader_stage target)
is_varying_var(ir_variable *var, mesa_shader_stage target)
{
switch (target) {
case MESA_SHADER_VERTEX:

4
src/compiler/glsl/gl_nir_link_uniform_blocks.c
View file

@ -1026,7 +1026,7 @@ fill_block(void *mem_ctx, const struct gl_constants *consts, const char *name,
unsigned binding_offset,
unsigned linearized_index,
struct gl_shader_program *prog,
const gl_shader_stage stage,
const mesa_shader_stage stage,
enum block_type block_type)
{
struct gl_uniform_block *block = &blocks[*block_index];
@ -1136,7 +1136,7 @@ fill_block_array(struct uniform_block_array_elements *ub_array,
struct gl_uniform_buffer_variable *variables,
unsigned *variable_index, unsigned binding_offset,
struct gl_shader_program *prog,
const gl_shader_stage stage, enum block_type block_type,
const mesa_shader_stage stage, enum block_type block_type,
unsigned *block_index, unsigned first_index)
{
for (unsigned j = 0; j < ub_array->num_array_elements; j++) {

2
src/compiler/glsl/gl_nir_link_uniforms.c
View file

@ -1306,7 +1306,7 @@ static int
nir_link_uniform(const struct gl_constants *consts,
struct gl_shader_program *prog,
struct gl_program *stage_program,
gl_shader_stage stage,
mesa_shader_stage stage,
const struct glsl_type *type,
unsigned index_in_parent,
int location,

38
src/compiler/glsl/gl_nir_link_varyings.c
View file

@ -74,7 +74,7 @@ compare_attr(const void *a, const void *b)
* geometry shader inputs).
*/
static const struct glsl_type *
get_varying_type(const nir_variable *var, gl_shader_stage stage)
get_varying_type(const nir_variable *var, mesa_shader_stage stage)
{
const struct glsl_type *type = var->type;
if (nir_is_arrayed_io(var, stage)) {
@ -147,8 +147,8 @@ cross_validate_types_and_qualifiers(const struct gl_constants *consts,
struct gl_shader_program *prog,
const nir_variable *input,
const nir_variable *output,
gl_shader_stage consumer_stage,
gl_shader_stage producer_stage)
mesa_shader_stage consumer_stage,
mesa_shader_stage producer_stage)
{
/* Check that the types match between stages.
*/
@ -355,8 +355,8 @@ cross_validate_front_and_back_color(const struct gl_constants *consts,
const nir_variable *input,
const nir_variable *front_color,
const nir_variable *back_color,
gl_shader_stage consumer_stage,
gl_shader_stage producer_stage)
mesa_shader_stage consumer_stage,
mesa_shader_stage producer_stage)
{
if (front_color != NULL && front_color->data.assigned)
cross_validate_types_and_qualifiers(consts, prog, input, front_color,
@ -368,7 +368,7 @@ cross_validate_front_and_back_color(const struct gl_constants *consts,
}
static unsigned
compute_variable_location_slot(nir_variable *var, gl_shader_stage stage)
compute_variable_location_slot(nir_variable *var, mesa_shader_stage stage)
{
unsigned location_start = VARYING_SLOT_VAR0;
@ -416,7 +416,7 @@ check_location_aliasing(struct explicit_location_info explicit_locations[][4],
bool sample,
bool patch,
struct gl_shader_program *prog,
gl_shader_stage stage)
mesa_shader_stage stage)
{
unsigned last_comp;
unsigned base_type_bit_size;
@ -742,8 +742,8 @@ validate_explicit_variable_location(const struct gl_constants *consts,
bool
gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_constants *consts,
struct gl_shader_program *prog,
gl_shader_stage first_stage,
gl_shader_stage last_stage)
mesa_shader_stage first_stage,
mesa_shader_stage last_stage)
{
/* VS inputs and FS outputs are validated in
* assign_attribute_or_color_locations()
@ -755,7 +755,7 @@ gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_cons
struct explicit_location_info explicit_locations[MAX_VARYING][4];
gl_shader_stage stages[2] = { first_stage, last_stage };
mesa_shader_stage stages[2] = { first_stage, last_stage };
bool validate_stage[2] = { validate_first_stage, validate_last_stage };
nir_variable_mode var_mode[2] = { nir_var_shader_in, nir_var_shader_out };
@ -763,7 +763,7 @@ gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_cons
if (!validate_stage[i])
continue;
gl_shader_stage stage = stages[i];
mesa_shader_stage stage = stages[i];
struct gl_linked_shader *sh = prog->_LinkedShaders[stage];
assert(sh);
@ -2449,8 +2449,8 @@ struct varying_matches
*/
unsigned matches_capacity;
gl_shader_stage producer_stage;
gl_shader_stage consumer_stage;
mesa_shader_stage producer_stage;
mesa_shader_stage consumer_stage;
};
/**
@ -2514,8 +2514,8 @@ varying_matches_not_xfb_comparator(const void *x_generic, const void *y_generic)
}
static bool
is_unpackable_tess(gl_shader_stage producer_stage,
gl_shader_stage consumer_stage)
is_unpackable_tess(mesa_shader_stage producer_stage,
mesa_shader_stage consumer_stage)
{
if (consumer_stage == MESA_SHADER_TESS_EVAL ||
consumer_stage == MESA_SHADER_TESS_CTRL ||
@ -2529,8 +2529,8 @@ static void
init_varying_matches(void *mem_ctx, struct varying_matches *vm,
const struct gl_constants *consts,
const struct gl_extensions *exts,
gl_shader_stage producer_stage,
gl_shader_stage consumer_stage,
mesa_shader_stage producer_stage,
mesa_shader_stage consumer_stage,
bool sso)
{
/* Tessellation shaders treat inputs and outputs as shared memory and can
@ -3098,7 +3098,7 @@ struct tfeedback_candidate_generator_state {
*/
struct hash_table *tfeedback_candidates;
gl_shader_stage stage;
mesa_shader_stage stage;
/**
* Pointer to the toplevel variable that is being traversed.
@ -3895,7 +3895,7 @@ remove_unused_shader_inputs_and_outputs(struct gl_shader_program *prog,
static void
linker_error_io_limit_exceeded(struct gl_shader_program *prog, gl_api api,
gl_shader_stage stage, unsigned num_comps,
mesa_shader_stage stage, unsigned num_comps,
unsigned max_comps, const char *in_or_out_name)
{
if (api == API_OPENGLES2 || prog->IsES) {

4
src/compiler/glsl/gl_nir_link_varyings.h
View file

@ -229,8 +229,8 @@ gl_assign_attribute_or_color_locations(const struct gl_constants *consts,
bool
gl_nir_validate_first_and_last_interface_explicit_locations(const struct gl_constants *consts,
struct gl_shader_program *prog,
gl_shader_stage first_stage,
gl_shader_stage last_stage);
mesa_shader_stage first_stage,
mesa_shader_stage last_stage);
void
gl_nir_cross_validate_outputs_to_inputs(const struct gl_constants *consts,

12
src/compiler/glsl/gl_nir_linker.c
View file

@ -1061,7 +1061,7 @@ nir_build_program_resource_list(const struct gl_constants *consts,
continue;
GLenum type =
_mesa_shader_stage_to_subroutine_uniform((gl_shader_stage)j);
_mesa_shader_stage_to_subroutine_uniform((mesa_shader_stage)j);
/* add shader subroutines */
if (!link_util_add_program_resource(prog, resource_set,
type, uniform, 0))
@ -1130,7 +1130,7 @@ nir_build_program_resource_list(const struct gl_constants *consts,
const int i = u_bit_scan(&mask);
struct gl_program *p = prog->_LinkedShaders[i]->Program;
GLuint type = _mesa_shader_stage_to_subroutine((gl_shader_stage)i);
GLuint type = _mesa_shader_stage_to_subroutine((mesa_shader_stage)i);
for (unsigned j = 0; j < p->sh.NumSubroutineFunctions; j++) {
if (!link_util_add_program_resource(prog, resource_set,
type,
@ -1282,7 +1282,7 @@ preprocess_shader(const struct pipe_screen *screen,
const struct gl_extensions *exts,
struct gl_program *prog,
struct gl_shader_program *shader_program,
gl_shader_stage stage)
mesa_shader_stage stage)
{
const struct gl_shader_compiler_options *gl_options =
&consts->ShaderCompilerOptions[prog->info.stage];
@ -3550,7 +3550,7 @@ gl_nir_link_glsl(struct gl_context *ctx, struct gl_shader_program *prog)
goto done;
}
gl_shader_stage shader_type = prog->Shaders[i]->Stage;
mesa_shader_stage shader_type = prog->Shaders[i]->Stage;
shader_list[shader_type][num_shaders[shader_type]] = prog->Shaders[i];
num_shaders[shader_type]++;
}
@ -3818,8 +3818,8 @@ gl_nir_link_glsl(struct gl_context *ctx, struct gl_shader_program *prog)
* is no cross validation for these.
*/
if (!gl_nir_validate_first_and_last_interface_explicit_locations(consts, prog,
(gl_shader_stage)first,
(gl_shader_stage)last))
(mesa_shader_stage)first,
(mesa_shader_stage)last))
goto done;
if (prog->SeparateShader)

2
src/compiler/glsl/gl_nir_lower_buffers.c
View file

@ -119,7 +119,7 @@ get_block_array_index(nir_builder *b, nir_deref_instr *deref,
static void
get_block_index_offset(nir_variable *var,
const struct gl_shader_program *shader_program,
gl_shader_stage stage,
mesa_shader_stage stage,
unsigned *index, unsigned *offset)
{

2
src/compiler/glsl/gl_nir_lower_samplers_as_deref.c
View file

@ -148,7 +148,7 @@ lower_deref(nir_builder *b, struct lower_samplers_as_deref_state *state,
nir_deref_instr *deref)
{
nir_variable *var = nir_deref_instr_get_variable(deref);
gl_shader_stage stage = state->shader->info.stage;
mesa_shader_stage stage = state->shader->info.stage;
if (!(var->data.mode & (nir_var_uniform | nir_var_image)) ||
var->data.bindless)

2
src/compiler/glsl/glsl_parser_extras.cpp
View file

@ -61,7 +61,7 @@ static const unsigned known_desktop_gl_versions[] =
_mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context *_ctx,
gl_shader_stage stage,
mesa_shader_stage stage,
void *mem_ctx)
: ctx(_ctx), exts(&_ctx->Extensions), consts(&_ctx->Const),
api(_ctx->API), cs_input_local_size_specified(false), cs_input_local_size(),

4
src/compiler/glsl/glsl_parser_extras.h
View file

@ -81,7 +81,7 @@ extern void _mesa_glsl_error(YYLTYPE *locp, _mesa_glsl_parse_state *state,
struct _mesa_glsl_parse_state {
_mesa_glsl_parse_state(struct gl_context *_ctx, gl_shader_stage stage,
_mesa_glsl_parse_state(struct gl_context *_ctx, mesa_shader_stage stage,
void *mem_ctx);
DECLARE_RZALLOC_CXX_OPERATORS(_mesa_glsl_parse_state);
@ -404,7 +404,7 @@ struct _mesa_glsl_parse_state {
/* Bitfield of ir_variable_mode to zero init */
uint32_t zero_init;
unsigned gl_version;
gl_shader_stage stage;
mesa_shader_stage stage;
/**
* Default uniform layout qualifiers tracked during parsing.

4
src/compiler/glsl/lower_vector_derefs.cpp
View file

@ -32,7 +32,7 @@ namespace {
class vector_deref_visitor : public ir_rvalue_enter_visitor {
public:
vector_deref_visitor(linear_ctx *linalloc, gl_shader_stage shader_stage)
vector_deref_visitor(linear_ctx *linalloc, mesa_shader_stage shader_stage)
: progress(false), shader_stage(shader_stage),
factory(&factory_instructions, linalloc)
{
@ -46,7 +46,7 @@ public:
virtual ir_visitor_status visit_enter(ir_assignment *ir);
bool progress;
gl_shader_stage shader_stage;
mesa_shader_stage shader_stage;
ir_exec_list factory_instructions;
ir_factory factory;
};

4
src/compiler/glsl/serialize.cpp
View file

@ -1234,7 +1234,7 @@ get_shader_info_and_pointer_sizes(size_t *s_info_size, size_t *s_info_ptrs,
static void
create_linked_shader_and_program(struct gl_context *ctx,
gl_shader_stage stage,
mesa_shader_stage stage,
struct gl_shader_program *prog,
struct blob_reader *metadata)
{
@ -1341,7 +1341,7 @@ deserialize_glsl_program(struct blob_reader *blob, struct gl_context *ctx,
unsigned mask = prog->data->linked_stages;
while (mask) {
const int j = u_bit_scan(&mask);
create_linked_shader_and_program(ctx, (gl_shader_stage) j, prog,
create_linked_shader_and_program(ctx, (mesa_shader_stage) j, prog,
blob);
}

6
src/compiler/glsl/standalone_scaffolding.cpp
View file

@ -104,7 +104,7 @@ _mesa_shader_debug(struct gl_context *, GLenum, GLuint *,
}
struct gl_shader *
_mesa_new_shader(GLuint name, gl_shader_stage stage)
_mesa_new_shader(GLuint name, mesa_shader_stage stage)
{
struct gl_shader *shader;
@ -181,7 +181,7 @@ _mesa_clear_shader_program_data(struct gl_context *ctx,
static void
init_gl_program(struct gl_program *prog, bool is_arb_asm, gl_shader_stage stage)
init_gl_program(struct gl_program *prog, bool is_arb_asm, mesa_shader_stage stage)
{
prog->RefCount = 1;
prog->Format = GL_PROGRAM_FORMAT_ASCII_ARB;
@ -190,7 +190,7 @@ init_gl_program(struct gl_program *prog, bool is_arb_asm, gl_shader_stage stage)
}
static struct gl_program *
standalone_new_program(UNUSED struct gl_context *ctx, gl_shader_stage stage,
standalone_new_program(UNUSED struct gl_context *ctx, mesa_shader_stage stage,
UNUSED GLuint id, bool is_arb_asm)
{
struct gl_program *prog = rzalloc(NULL, struct gl_program);

4
src/compiler/glsl/standalone_scaffolding.h
View file

@ -53,7 +53,7 @@ _mesa_reference_program_(struct gl_context *ctx, struct gl_program **ptr,
struct gl_program *prog);
extern "C" struct gl_shader *
_mesa_new_shader(GLuint name, gl_shader_stage stage);
_mesa_new_shader(GLuint name, mesa_shader_stage stage);
extern "C" void
_mesa_delete_shader(struct gl_context *ctx, struct gl_shader *sh);
@ -77,7 +77,7 @@ _mesa_program_state_flags(const gl_state_index16 state[STATE_LENGTH]);
extern "C" char *
_mesa_program_state_string(const gl_state_index16 state[STATE_LENGTH]);
static inline gl_shader_stage
static inline mesa_shader_stage
_mesa_shader_enum_to_shader_stage(GLenum v)
{
switch (v) {

12
src/compiler/nir/nir.c
View file

@ -195,7 +195,7 @@ nir_component_mask_reinterpret(nir_component_mask_t mask,
nir_shader *
nir_shader_create(void *mem_ctx,
gl_shader_stage stage,
mesa_shader_stage stage,
const nir_shader_compiler_options *options,
shader_info *si)
{
@ -3597,7 +3597,7 @@ nir_instr_xfb_write_mask(nir_intrinsic_instr *instr)
* Whether an output slot is consumed by fixed-function logic.
*/
bool
nir_slot_is_sysval_output(gl_varying_slot slot, gl_shader_stage next_shader)
nir_slot_is_sysval_output(gl_varying_slot slot, mesa_shader_stage next_shader)
{
switch (next_shader) {
case MESA_SHADER_FRAGMENT:
@ -3647,7 +3647,7 @@ nir_slot_is_sysval_output(gl_varying_slot slot, gl_shader_stage next_shader)
* Pass MESA_SHADER_NONE if the next shader is unknown.
*/
bool
nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader)
nir_slot_is_varying(gl_varying_slot slot, mesa_shader_stage next_shader)
{
bool unknown = next_shader == MESA_SHADER_NONE;
bool exactly_before_fs = next_shader == MESA_SHADER_FRAGMENT || unknown;
@ -3680,7 +3680,7 @@ nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader)
bool
nir_slot_is_sysval_output_and_varying(gl_varying_slot slot,
gl_shader_stage next_shader)
mesa_shader_stage next_shader)
{
return nir_slot_is_sysval_output(slot, next_shader) &&
nir_slot_is_varying(slot, next_shader);
@ -3691,7 +3691,7 @@ nir_slot_is_sysval_output_and_varying(gl_varying_slot slot,
* stage. If the instruction has no other use, it's removed.
*/
bool
nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader)
nir_remove_varying(nir_intrinsic_instr *intr, mesa_shader_stage next_shader)
{
nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
@ -3713,7 +3713,7 @@ nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader)
* logic. If the instruction has no other use, it's removed.
*/
bool
nir_remove_sysval_output(nir_intrinsic_instr *intr, gl_shader_stage next_shader)
nir_remove_sysval_output(nir_intrinsic_instr *intr, mesa_shader_stage next_shader)
{
nir_io_semantics sem = nir_intrinsic_io_semantics(intr);

16
src/compiler/nir/nir.h
View file

@ -3937,7 +3937,7 @@ void nir_remove_entrypoints(nir_shader *shader);
void nir_fixup_is_exported(nir_shader *shader);
nir_shader *nir_shader_create(void *mem_ctx,
gl_shader_stage stage,
mesa_shader_stage stage,
const nir_shader_compiler_options *options,
shader_info *si);
@ -5063,12 +5063,12 @@ nir_opt_varyings_bulk(nir_shader **shaders, uint32_t num_shaders, bool spirv,
void (*optimize)(nir_shader *));
bool nir_slot_is_sysval_output(gl_varying_slot slot,
gl_shader_stage next_shader);
bool nir_slot_is_varying(gl_varying_slot slot, gl_shader_stage next_shader);
mesa_shader_stage next_shader);
bool nir_slot_is_varying(gl_varying_slot slot, mesa_shader_stage next_shader);
bool nir_slot_is_sysval_output_and_varying(gl_varying_slot slot,
gl_shader_stage next_shader);
bool nir_remove_varying(nir_intrinsic_instr *intr, gl_shader_stage next_shader);
bool nir_remove_sysval_output(nir_intrinsic_instr *intr, gl_shader_stage next_shader);
mesa_shader_stage next_shader);
bool nir_remove_varying(nir_intrinsic_instr *intr, mesa_shader_stage next_shader);
bool nir_remove_sysval_output(nir_intrinsic_instr *intr, mesa_shader_stage next_shader);
bool nir_lower_amul(nir_shader *shader,
int (*type_size)(const struct glsl_type *, bool));
@ -5079,7 +5079,7 @@ void nir_sort_variables_by_location(nir_shader *shader, nir_variable_mode mode);
void nir_assign_io_var_locations(nir_shader *shader,
nir_variable_mode mode,
unsigned *size,
gl_shader_stage stage);
mesa_shader_stage stage);
bool nir_opt_clip_cull_const(nir_shader *shader);
@ -5318,7 +5318,7 @@ nir_src *nir_get_io_arrayed_index_src(nir_intrinsic_instr *instr);
nir_src *nir_get_shader_call_payload_src(nir_intrinsic_instr *call);
bool nir_is_output_load(nir_intrinsic_instr *intr);
bool nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage);
bool nir_is_arrayed_io(const nir_variable *var, mesa_shader_stage stage);
bool nir_lower_reg_intrinsics_to_ssa_impl(nir_function_impl *impl);
bool nir_lower_reg_intrinsics_to_ssa(nir_shader *shader);

2
src/compiler/nir/nir_builder.c
View file

@ -31,7 +31,7 @@
#include "nir_serialize.h"
nir_builder MUST_CHECK PRINTFLIKE(3, 4)
nir_builder_init_simple_shader(gl_shader_stage stage,
nir_builder_init_simple_shader(mesa_shader_stage stage,
const nir_shader_compiler_options *options,
const char *name, ...)
{

2
src/compiler/nir/nir_builder.h
View file

@ -70,7 +70,7 @@ nir_builder_at(nir_cursor cursor)
}
nir_builder MUST_CHECK PRINTFLIKE(3, 4)
nir_builder_init_simple_shader(gl_shader_stage stage,
nir_builder_init_simple_shader(mesa_shader_stage stage,
const nir_shader_compiler_options *options,
const char *name, ...);

6
src/compiler/nir/nir_divergence_analysis.c
View file

@ -39,7 +39,7 @@
*/
struct divergence_state {
const gl_shader_stage stage;
const mesa_shader_stage stage;
nir_shader *shader;
nir_function_impl *impl;
nir_divergence_options options;
@ -180,7 +180,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
return false;
nir_divergence_options options = state->options;
gl_shader_stage stage = state->stage;
mesa_shader_stage stage = state->stage;
bool is_divergent = false;
switch (instr->intrinsic) {
case nir_intrinsic_shader_clock:
@ -1059,7 +1059,7 @@ nir_variable_is_uniform(nir_shader *shader, nir_variable *var,
}
nir_divergence_options options = state->options;
gl_shader_stage stage = shader->info.stage;
mesa_shader_stage stage = shader->info.stage;
if (stage == MESA_SHADER_FRAGMENT &&
(options & nir_divergence_single_prim_per_subgroup) &&

8
src/compiler/nir/nir_linking_helpers.c
View file

@ -36,7 +36,7 @@
* bitfield corresponding to this variable.
*/
static uint64_t
get_variable_io_mask(nir_variable *var, gl_shader_stage stage)
get_variable_io_mask(nir_variable *var, mesa_shader_stage stage)
{
if (var->data.location < 0)
return 0;
@ -326,7 +326,7 @@ static void
get_unmoveable_components_masks(nir_shader *shader,
nir_variable_mode mode,
struct assigned_comps *comps,
gl_shader_stage stage,
mesa_shader_stage stage,
bool default_to_smooth_interp)
{
nir_foreach_variable_with_modes_safe(var, shader, mode) {
@ -423,7 +423,7 @@ remap_slots_and_components(nir_shader *shader, nir_variable_mode mode,
uint64_t *slots_used, uint64_t *out_slots_read,
uint32_t *p_slots_used, uint32_t *p_out_slots_read)
{
const gl_shader_stage stage = shader->info.stage;
const mesa_shader_stage stage = shader->info.stage;
uint64_t out_slots_read_tmp[2] = { 0 };
uint64_t slots_used_tmp[2] = { 0 };
@ -1484,7 +1484,7 @@ nir_sort_variables_by_location(nir_shader *shader, nir_variable_mode mode)
void
nir_assign_io_var_locations(nir_shader *shader, nir_variable_mode mode,
unsigned *size, gl_shader_stage stage)
unsigned *size, mesa_shader_stage stage)
{
unsigned location = 0;
unsigned assigned_locations[VARYING_SLOT_TESS_MAX][2];

2
src/compiler/nir/nir_lower_clip_cull_distance_array_vars.c
View file

@ -81,7 +81,7 @@ struct lower_distance_state {
/**
* Type of shader we are compiling (e.g. MESA_SHADER_VERTEX)
*/
gl_shader_stage shader_stage;
mesa_shader_stage shader_stage;
const char *in_name;
int total_size;
int offset;

2
src/compiler/nir/nir_lower_io.c
View file

@ -64,7 +64,7 @@ add_variable_name(struct lower_io_state *state, const char *name)
* the vertex index within the primitive.
*/
bool
nir_is_arrayed_io(const nir_variable *var, gl_shader_stage stage)
nir_is_arrayed_io(const nir_variable *var, mesa_shader_stage stage)
{
if (var->data.patch || !glsl_type_is_array(var->type))
return false;

2
src/compiler/nir/nir_lower_io_array_vars_to_elements.c
View file

@ -81,7 +81,7 @@ get_io_offset(nir_builder *b, nir_deref_instr *deref, nir_variable *var,
static nir_variable **
get_array_elements(struct hash_table *ht, nir_variable *var,
gl_shader_stage stage)
mesa_shader_stage stage)
{
nir_variable **elements;
struct hash_entry *entry = _mesa_hash_table_search(ht, var);

2
src/compiler/nir/nir_lower_io_indirect_loads.c
View file

@ -74,7 +74,7 @@ get_load_var(nir_intrinsic_instr *intr, lower_io_indir_loads_state *state)
}
static nir_variable **
get_load_once_variable(gl_shader_stage stage, nir_intrinsic_instr *intr,
get_load_once_variable(mesa_shader_stage stage, nir_intrinsic_instr *intr,
lower_io_indir_loads_state *state)
{
if (intr->intrinsic == nir_intrinsic_load_interpolated_input) {

4
src/compiler/nir/nir_opt_varyings.c
View file

@ -660,8 +660,8 @@ struct linkage_info {
bool always_interpolate_convergent_fs_inputs;
bool group_tes_inputs_into_pos_var_groups;
gl_shader_stage producer_stage;
gl_shader_stage consumer_stage;
mesa_shader_stage producer_stage;
mesa_shader_stage consumer_stage;
nir_builder producer_builder;
nir_builder consumer_builder;
unsigned max_varying_expression_cost;

2
src/compiler/nir/nir_precompiled.h
View file

@ -628,7 +628,7 @@ nir_precomp_print_target_binary_map(FILE *fp_c, FILE *fp_h, const char *prefix,
static inline nir_shader *
nir_precompiled_build_variant(const nir_function *libfunc,
gl_shader_stage stage, unsigned variant,
mesa_shader_stage stage, unsigned variant,
const nir_shader_compiler_options *opts,
const struct nir_precomp_opts *precomp_opt,
nir_def *(*load_arg)(nir_builder *b,

2
src/compiler/nir/nir_print.c
View file

@ -776,7 +776,7 @@ get_variable_mode_str(nir_variable_mode mode, bool want_local_global_mode)
}
static const char *
get_location_str(unsigned location, gl_shader_stage stage,
get_location_str(unsigned location, mesa_shader_stage stage,
nir_variable_mode mode, char *buf)
{
switch (stage) {

4
src/compiler/nir/tests/nir_opt_varyings_test.h
View file

@ -76,8 +76,8 @@ protected:
return UINT_MAX;
}
void create_shaders(gl_shader_stage producer_stage,
gl_shader_stage consumer_stage)
void create_shaders(mesa_shader_stage producer_stage,
mesa_shader_stage consumer_stage)
{
_producer_builder =
nir_builder_init_simple_shader(producer_stage, &options,

2
src/compiler/nir/tests/nir_test.h
View file

@ -25,7 +25,7 @@ class nir_test : public ::testing::Test {
{
}
nir_test(const char *name, gl_shader_stage stage)
nir_test(const char *name, mesa_shader_stage stage)
{
glsl_type_singleton_init_or_ref();

2
src/compiler/rust/meson.build
View file

@ -19,7 +19,7 @@ _compiler_binding_types = [
'gl_access_qualifier',
'gl_frag_result',
'gl_interp_mode',
'gl_shader_stage',
'mesa_shader_stage',
'gl_subgroup_size',
'gl_system_value',
'gl_tess_spacing',

8
src/compiler/shader_enums.c
View file

@ -34,7 +34,7 @@
#define NAME(val) ((((val) < ARRAY_SIZE(names)) && names[(val)]) ? names[(val)] : "UNKNOWN")
const char *
gl_shader_stage_name(gl_shader_stage stage)
gl_shader_stage_name(mesa_shader_stage stage)
{
static const char *names[] = {
ENUM(MESA_SHADER_VERTEX),
@ -58,7 +58,7 @@ gl_shader_stage_name(gl_shader_stage stage)
}
/**
* Translate a gl_shader_stage to a short shader stage name for debug
* Translate a mesa_shader_stage to a short shader stage name for debug
* printouts and error messages.
*/
const char *
@ -86,7 +86,7 @@ _mesa_shader_stage_to_string(unsigned stage)
}
/**
* Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
* Translate a mesa_shader_stage to a shader stage abbreviation (VS, GS, FS)
* for debug printouts and error messages.
*/
const char *
@ -155,7 +155,7 @@ gl_vert_attrib_name(gl_vert_attrib attrib)
}
const char *
gl_varying_slot_name_for_stage(gl_varying_slot slot, gl_shader_stage stage)
gl_varying_slot_name_for_stage(gl_varying_slot slot, mesa_shader_stage stage)
{
if (stage != MESA_SHADER_FRAGMENT && slot == VARYING_SLOT_PRIMITIVE_SHADING_RATE)
return "VARYING_SLOT_PRIMITIVE_SHADING_RATE";

24
src/compiler/shader_enums.h
View file

@ -82,23 +82,23 @@ typedef enum pipe_shader_type
/* must be last so it doesn't affect the GL pipeline */
MESA_SHADER_KERNEL = 14,
} gl_shader_stage;
} mesa_shader_stage;
static inline bool
gl_shader_stage_is_compute(gl_shader_stage stage)
gl_shader_stage_is_compute(mesa_shader_stage stage)
{
return stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL;
}
static inline bool
gl_shader_stage_is_mesh(gl_shader_stage stage)
gl_shader_stage_is_mesh(mesa_shader_stage stage)
{
return stage == MESA_SHADER_TASK ||
stage == MESA_SHADER_MESH;
}
static inline bool
gl_shader_stage_is_graphics(gl_shader_stage stage)
gl_shader_stage_is_graphics(mesa_shader_stage stage)
{
switch (stage) {
case MESA_SHADER_VERTEX:
@ -115,7 +115,7 @@ gl_shader_stage_is_graphics(gl_shader_stage stage)
}
static inline bool
gl_shader_stage_uses_workgroup(gl_shader_stage stage)
gl_shader_stage_uses_workgroup(mesa_shader_stage stage)
{
return stage == MESA_SHADER_COMPUTE ||
stage == MESA_SHADER_KERNEL ||
@ -124,7 +124,7 @@ gl_shader_stage_uses_workgroup(gl_shader_stage stage)
}
static inline bool
gl_shader_stage_is_callable(gl_shader_stage stage)
gl_shader_stage_is_callable(mesa_shader_stage stage)
{
return stage == MESA_SHADER_ANY_HIT ||
stage == MESA_SHADER_CLOSEST_HIT ||
@ -134,13 +134,13 @@ gl_shader_stage_is_callable(gl_shader_stage stage)
}
static inline bool
gl_shader_stage_is_rt(gl_shader_stage stage)
gl_shader_stage_is_rt(mesa_shader_stage stage)
{
return stage == MESA_SHADER_RAYGEN || gl_shader_stage_is_callable(stage);
}
static inline bool
gl_shader_stage_can_set_fragment_shading_rate(gl_shader_stage stage)
gl_shader_stage_can_set_fragment_shading_rate(mesa_shader_stage stage)
{
/* According to EXT_fragment_shading_rate :
*
@ -160,16 +160,16 @@ gl_shader_stage_can_set_fragment_shading_rate(gl_shader_stage stage)
typedef short gl_state_index16; /* see enum gl_state_index */
const char *gl_shader_stage_name(gl_shader_stage stage);
const char *gl_shader_stage_name(mesa_shader_stage stage);
/**
* Translate a gl_shader_stage to a short shader stage name for debug
* Translate a mesa_shader_stage to a short shader stage name for debug
* printouts and error messages.
*/
const char *_mesa_shader_stage_to_string(unsigned stage);
/**
* Translate a gl_shader_stage to a shader stage abbreviation (VS, GS, FS)
* Translate a mesa_shader_stage to a shader stage abbreviation (VS, GS, FS)
* for debug printouts and error messages.
*/
const char *_mesa_shader_stage_to_abbrev(unsigned stage);
@ -485,7 +485,7 @@ typedef enum
#define MAX_VARYINGS_INCL_PATCH (VARYING_SLOT_TESS_MAX - VARYING_SLOT_VAR0)
const char *gl_varying_slot_name_for_stage(gl_varying_slot slot,
gl_shader_stage stage);
mesa_shader_stage stage);
/**
* Determine if the given gl_varying_slot appears in the fragment shader.

6
src/compiler/shader_info.h
View file

@ -50,13 +50,13 @@ typedef struct shader_info {
blake3_hash source_blake3;
/** The shader stage, such as MESA_SHADER_VERTEX. */
gl_shader_stage stage:8;
mesa_shader_stage stage:8;
/* If the shader is linked, this is the previous shader, else MESA_SHADER_NONE. */
gl_shader_stage prev_stage:8;
mesa_shader_stage prev_stage:8;
/* If the shader is linked, this is the next shader, else MESA_SHADER_NONE. */
gl_shader_stage next_stage:8;
mesa_shader_stage next_stage:8;
/* Whether the previous stage has XFB if the shader is linked (prev_stage != NONE). */
bool prev_stage_has_xfb;

2
src/compiler/spirv/gl_spirv.c
View file

@ -230,7 +230,7 @@ enum spirv_verify_result
spirv_verify_gl_specialization_constants(
const uint32_t *words, size_t word_count,
struct nir_spirv_specialization *spec, unsigned num_spec,
gl_shader_stage stage, const char *entry_point_name)
mesa_shader_stage stage, const char *entry_point_name)
{
/* vtn_warn/vtn_log uses debug.func. Setting a null to prevent crash. Not
* need to print the warnings now, would be done later, on the real

4
src/compiler/spirv/nir_spirv.h
View file

@ -164,12 +164,12 @@ enum spirv_verify_result {
enum spirv_verify_result spirv_verify_gl_specialization_constants(
const uint32_t *words, size_t word_count,
struct nir_spirv_specialization *spec, unsigned num_spec,
gl_shader_stage stage, const char *entry_point_name);
mesa_shader_stage stage, const char *entry_point_name);
nir_shader *spirv_to_nir(const uint32_t *words, size_t word_count,
struct nir_spirv_specialization *specializations,
unsigned num_specializations,
gl_shader_stage stage, const char *entry_point_name,
mesa_shader_stage stage, const char *entry_point_name,
const struct spirv_to_nir_options *options,
const nir_shader_compiler_options *nir_options);

12
src/compiler/spirv/spirv2nir.c
View file

@ -46,7 +46,7 @@
struct {
const char *name;
gl_shader_stage stage;
mesa_shader_stage stage;
} abbrev_stage_table[] = {
{ "vs", MESA_SHADER_VERTEX },
{ "tcs", MESA_SHADER_TESS_CTRL },
@ -68,7 +68,7 @@ struct {
{ "kernel", MESA_SHADER_KERNEL },
};
static gl_shader_stage
static mesa_shader_stage
abbrev_to_stage(const char *name)
{
for (unsigned i = 0; i < ARRAY_SIZE(abbrev_stage_table); i++) {
@ -79,7 +79,7 @@ abbrev_to_stage(const char *name)
}
static const char *
stage_to_abbrev(gl_shader_stage stage)
stage_to_abbrev(mesa_shader_stage stage)
{
for (unsigned i = 0; i < ARRAY_SIZE(abbrev_stage_table); i++) {
if (abbrev_stage_table[i].stage == stage)
@ -111,7 +111,7 @@ print_usage(char *exec_name, FILE *f)
struct entry_point {
const char *name;
gl_shader_stage stage;
mesa_shader_stage stage;
};
static struct entry_point
@ -139,7 +139,7 @@ select_entry_point(void *mem_ctx, const uint32_t *words, size_t word_count,
unsigned name_words;
const char *name = vtn_string_literal(b, &w[3], count - 3, &name_words);
gl_shader_stage stage = vtn_stage_for_execution_model(w[1]);
mesa_shader_stage stage = vtn_stage_for_execution_model(w[1]);
struct entry_point e = { name, stage };
util_dynarray_append(&candidates, struct entry_point, e);
@ -214,7 +214,7 @@ int main(int argc, char **argv)
print_usage(argv[0], stdout);
return 0;
case 's': {
gl_shader_stage s = abbrev_to_stage(optarg);
mesa_shader_stage s = abbrev_to_stage(optarg);
if (s == MESA_SHADER_NONE) {
fprintf(stderr, "Unknown stage \"%s\"\n", optarg);
print_usage(argv[0], stderr);

8
src/compiler/spirv/spirv_to_nir.c
View file

@ -5081,7 +5081,7 @@ vertices_in_from_spv_execution_mode(struct vtn_builder *b,
}
}
gl_shader_stage
mesa_shader_stage
vtn_stage_for_execution_model(SpvExecutionModel model)
{
switch (model) {
@ -5132,7 +5132,7 @@ vtn_handle_entry_point(struct vtn_builder *b, const uint32_t *w,
entry_point->name = vtn_string_literal(b, &w[3], count - 3, &name_words);
entry_point->is_entrypoint = true;
gl_shader_stage stage = vtn_stage_for_execution_model(w[1]);
mesa_shader_stage stage = vtn_stage_for_execution_model(w[1]);
vtn_fail_if(stage == MESA_SHADER_NONE,
"Unsupported execution model: %s (%u)",
spirv_executionmodel_to_string(w[1]), w[1]);
@ -6952,7 +6952,7 @@ is_glslang(const struct vtn_builder *b)
struct vtn_builder*
vtn_create_builder(const uint32_t *words, size_t word_count,
gl_shader_stage stage, const char *entry_point_name,
mesa_shader_stage stage, const char *entry_point_name,
const struct spirv_to_nir_options *options)
{
/* Initialize the vtn_builder object */
@ -7197,7 +7197,7 @@ can_remove(nir_variable *var, void *data)
nir_shader *
spirv_to_nir(const uint32_t *words, size_t word_count,
struct nir_spirv_specialization *spec, unsigned num_spec,
gl_shader_stage stage, const char *entry_point_name,
mesa_shader_stage stage, const char *entry_point_name,
const struct spirv_to_nir_options *options,
const nir_shader_compiler_options *nir_options)

2
src/compiler/spirv/tests/helpers.h
View file

@ -60,7 +60,7 @@ protected:
glsl_type_singleton_decref();
}
void get_nir(size_t num_words, const uint32_t *words, gl_shader_stage stage = MESA_SHADER_COMPUTE)
void get_nir(size_t num_words, const uint32_t *words, mesa_shader_stage stage = MESA_SHADER_COMPUTE)
{
shader = spirv_to_nir(words, num_words, NULL, 0,
stage, "main", &spirv_options, &nir_options);

6
src/compiler/spirv/vtn_private.h
View file

@ -690,7 +690,7 @@ struct vtn_builder {
/* Workaround discard bugs in HLSL -> SPIR-V compilers */
bool convert_discard_to_demote;
gl_shader_stage entry_point_stage;
mesa_shader_stage entry_point_stage;
const char *entry_point_name;
struct vtn_value *entry_point;
struct vtn_value *workgroup_size_builtin;
@ -1003,7 +1003,7 @@ bool vtn_handle_opencl_core_instruction(struct vtn_builder *b, SpvOp opcode,
const uint32_t *w, unsigned count);
struct vtn_builder* vtn_create_builder(const uint32_t *words, size_t word_count,
gl_shader_stage stage, const char *entry_point_name,
mesa_shader_stage stage, const char *entry_point_name,
const struct spirv_to_nir_options *options);
void vtn_handle_entry_point(struct vtn_builder *b, const uint32_t *w,
@ -1106,6 +1106,6 @@ struct vtn_ssa_value *vtn_cooperative_matrix_insert(struct vtn_builder *b, struc
nir_deref_instr *vtn_create_cmat_temporary(struct vtn_builder *b,
const struct glsl_type *t, const char *name);
gl_shader_stage vtn_stage_for_execution_model(SpvExecutionModel model);
mesa_shader_stage vtn_stage_for_execution_model(SpvExecutionModel model);
#endif /* _VTN_PRIVATE_H_ */

2
src/freedreno/common/disasm.h
View file

@ -36,7 +36,7 @@ struct shader_stats {
};
int disasm_a2xx(uint32_t *dwords, int sizedwords, int level,
gl_shader_stage type);
mesa_shader_stage type);
int disasm_a3xx(uint32_t *dwords, int sizedwords, int level, FILE *out,
unsigned gpu_id);
int disasm_a3xx_stat(uint32_t *dwords, int sizedwords, int level, FILE *out,

16
src/freedreno/decode/cffdec.c
View file

@ -1209,7 +1209,7 @@ cp_im_loadi(uint32_t *dwords, uint32_t sizedwords, int level)
uint32_t start = dwords[1] >> 16;
uint32_t size = dwords[1] & 0xffff;
const char *type = NULL, *ext = NULL;
gl_shader_stage disasm_type;
mesa_shader_stage disasm_type;
switch (dwords[0]) {
case 0:
@ -1286,13 +1286,13 @@ enum adreno_state_block {
*/
static void
a3xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage,
a3xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage,
enum state_t *state, enum state_src_t *src)
{
unsigned state_block_id = (dwords[0] >> 19) & 0x7;
unsigned state_type = dwords[1] & 0x3;
static const struct {
gl_shader_stage stage;
mesa_shader_stage stage;
enum state_t state;
} lookup[0xf][0x3] = {
[SB_VERT_TEX][0] = {MESA_SHADER_VERTEX, TEX_SAMP},
@ -1331,10 +1331,10 @@ _get_state_src(unsigned dword0)
static void
_get_state_type(unsigned state_block_id, unsigned state_type,
gl_shader_stage *stage, enum state_t *state)
mesa_shader_stage *stage, enum state_t *state)
{
static const struct {
gl_shader_stage stage;
mesa_shader_stage stage;
enum state_t state;
} lookup[0x10][0x4] = {
// SB4_VS_TEX:
@ -1407,7 +1407,7 @@ _get_state_type(unsigned state_block_id, unsigned state_type,
}
static void
a4xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage,
a4xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage,
enum state_t *state, enum state_src_t *src)
{
unsigned state_block_id = (dwords[0] >> 18) & 0xf;
@ -1417,7 +1417,7 @@ a4xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage,
}
static void
a6xx_get_state_type(uint32_t *dwords, gl_shader_stage *stage,
a6xx_get_state_type(uint32_t *dwords, mesa_shader_stage *stage,
enum state_t *state, enum state_src_t *src)
{
unsigned state_block_id = (dwords[0] >> 18) & 0xf;
@ -1568,7 +1568,7 @@ dump_bindless_descriptors(bool is_compute, int level)
static void
cp_load_state(uint32_t *dwords, uint32_t sizedwords, int level)
{
gl_shader_stage stage;
mesa_shader_stage stage;
enum state_t state;
enum state_src_t src;
uint32_t num_unit = (dwords[0] >> 22) & 0x1ff;

2
src/freedreno/decode/pgmdump.c
View file

@ -1000,7 +1000,7 @@ main(int argc, char **argv)
/* figure out what sort of input we are dealing with: */
if (!(check_extension(infile, ".rd") || check_extension(infile, ".rd.gz"))) {
gl_shader_stage shader = ~0;
mesa_shader_stage shader = ~0;
int ret;
if (check_extension(infile, ".vo")) {
shader = MESA_SHADER_VERTEX;

6
src/freedreno/ir2/disasm-a2xx.c
View file

@ -87,7 +87,7 @@ print_dstreg(uint32_t num, uint32_t mask, uint32_t dst_exp)
}
static void
print_export_comment(uint32_t num, gl_shader_stage type)
print_export_comment(uint32_t num, mesa_shader_stage type)
{
const char *name = NULL;
switch (type) {
@ -210,7 +210,7 @@ struct {
static int
disasm_alu(uint32_t *dwords, uint32_t alu_off, int level, int sync,
gl_shader_stage type)
mesa_shader_stage type)
{
instr_alu_t *alu = (instr_alu_t *)dwords;
@ -600,7 +600,7 @@ print_cf(instr_cf_t *cf, int level)
*/
int
disasm_a2xx(uint32_t *dwords, int sizedwords, int level, gl_shader_stage type)
disasm_a2xx(uint32_t *dwords, int sizedwords, int level, mesa_shader_stage type)
{
instr_cf_t *cfs = (instr_cf_t *)dwords;
int idx, max_idx;

2
src/freedreno/ir3/ir3.h
View file

@ -619,7 +619,7 @@ struct ir3_instruction_rpt {
struct ir3 {
struct ir3_compiler *compiler;
gl_shader_stage type;
mesa_shader_stage type;
DECLARE_ARRAY(struct ir3_instruction *, inputs);

2
src/freedreno/ir3/ir3_compiler.h
View file

@ -393,7 +393,7 @@ extern enum ir3_shader_debug ir3_shader_debug;
extern const char *ir3_shader_override_path;
static inline bool
shader_debug_enabled(gl_shader_stage type, bool internal)
shader_debug_enabled(mesa_shader_stage type, bool internal)
{
if (internal)
return !!(ir3_shader_debug & IR3_DBG_SHADER_INTERNAL);

4
src/freedreno/ir3/ir3_legalize.c
View file

@ -30,7 +30,7 @@
struct ir3_legalize_ctx {
struct ir3_compiler *compiler;
struct ir3_shader_variant *so;
gl_shader_stage type;
mesa_shader_stage type;
int max_bary;
bool early_input_release;
bool has_inputs;
@ -427,7 +427,7 @@ ir3_merge_pred_legalize_states(struct ir3_legalize_state *state,
&pstate->needs_ss_or_sy_scalar_war);
}
gl_shader_stage stage = block->shader->type;
mesa_shader_stage stage = block->shader->type;
if (stage == MESA_SHADER_TESS_CTRL || stage == MESA_SHADER_GEOMETRY) {
if (block == ir3_start_block(block->shader)) {

4
src/freedreno/ir3/ir3_nir.c
View file

@ -968,7 +968,7 @@ lower_ucp_vs(struct ir3_shader_variant *so)
if (!so->key.ucp_enables)
return false;
gl_shader_stage last_geom_stage;
mesa_shader_stage last_geom_stage;
if (so->key.has_gs) {
last_geom_stage = MESA_SHADER_GEOMETRY;
@ -1508,7 +1508,7 @@ void
ir3_alloc_driver_params(struct ir3_const_allocations *const_alloc,
uint32_t *num_driver_params,
struct ir3_compiler *compiler,
gl_shader_stage shader_stage)
mesa_shader_stage shader_stage)
{
if (*num_driver_params == 0)
return;

2
src/freedreno/ir3/ir3_ra.c
View file

@ -348,7 +348,7 @@ struct ra_ctx {
struct ir3_block *block;
const struct ir3_compiler *compiler;
gl_shader_stage stage;
mesa_shader_stage stage;
/* Pending moves of top-level intervals that will be emitted once we're
* finished:

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