Commit graph

219262 commits

Author SHA1 Message Date
Pierre-Eric Pelloux-Prayer
fea431ded3 radeonsi: remove nir references when graphics is disabled
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:58 +01:00
Pierre-Eric Pelloux-Prayer
4dc706ed5a radeonsi: use with_gfx_compute to disable parts of the driver
The disabled parts are unused when GL is disabled.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:56 +01:00
Pierre-Eric Pelloux-Prayer
c446582680 meson: add with_gfx_compute property
When none of Vulkan, GL, rusticl and VA are enabled, with_gfx_compute is
false and HAVE_GFX_COMPUTE isn't defined.

This can then be used to disable parts of drivers.

For now it's not really useful, as the resulting build cannot do anything.
Later, a new option will allow disabling the VA features that require
shader support so we can build a minimal VA driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:53 +01:00
Pierre-Eric Pelloux-Prayer
6af779e6bc ac: add u_stub.h helper
And use it from ac_linux_drm.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:51 +01:00
Pierre-Eric Pelloux-Prayer
731006bb8b radeonsi: move si_ps_key_update_framebuffer to si_state.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:50 +01:00
Pierre-Eric Pelloux-Prayer
b3cbc38a42 radeonsi: move buffer high-level functions to si_buffer.c
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:48 +01:00
Pierre-Eric Pelloux-Prayer
b97a6ae5ef radeonsi: split shaders/draw code from si_debug to a new file
Anything that depends on shaders is now part of si_debug_gfx_compute.c

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:45 +01:00
Pierre-Eric Pelloux-Prayer
15d52dff45 radeonsi: move mediump code to a separate compilation unit
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:43 +01:00
Pierre-Eric Pelloux-Prayer
9f06177599 ac: keep a single instance of sid_table
3 files include sid_tables.h so it means we had 3 copies of all
its static content. This removes ~260kB from libgallium and
libvulkan_radeon.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39482>
2026-03-02 09:53:40 +01:00
Christian Gmeiner
6135052145 etnaviv: Add S8_UINT texture format support for stencil texturing
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On GPUs with ETNA_FEATURE_S8, the hardware supports native 8bpp
stencil buffers. The blob driver samples these as R8I (8-bit integer).

This enables the stencil blit fallback to work with pure S8_UINT
stencil buffers, fixing
dEQP-GLES3.functional.fbo.blit.depth_stencil.stencil_index8_scale

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
2026-03-02 08:01:01 +00:00
Christian Gmeiner
ee7583a666 etnaviv: Implement stencil-only blit using util_blitter fallback
Previously, stencil-only blits were silently skipped with "cannot blit
stencil, skipping" because neither the BLT nor RS engines can
selectively copy individual channels from packed depth/stencil formats.

On HALTI5+ GPUs that support stencil texturing (S8X24_UINT), use
util_blitter_stencil_fallback() to perform a shader-based stencil blit.
This clears the destination stencil to zero, then copies each stencil
bit individually using draw calls with per-bit DSA write masks.

Fixes dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_stencil_only

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
2026-03-02 08:01:01 +00:00
Christian Gmeiner
7d7c164024 etnaviv: Mark TS config dirty after BLT blit
After a BLT blit invalidates the destination's tile status,
ETNA_DIRTY_DERIVE_TS was not set, so etna_update_ts_config() would not
run before the next draw. This caused TS_MEM_CONFIG to retain stale
DEPTH_FAST_CLEAR/DEPTH_COMPRESSION bits from the previous draw, even
though the destination depth data was overwritten by the blit.

This fixes depth/stencil blit tests like
dEQP-GLES3.functional.fbo.blit.depth_stencil.depth24_stencil8_basic.

The RS blit path already sets this dirty bit.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39936>
2026-03-02 08:01:00 +00:00
Lionel Landwerlin
0b1d1dc61b docs/anv: add some debug tips
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40134>
2026-03-02 07:30:34 +00:00
Rob Clark
1e1d8931c7 freedreno: Reduce advertised memory
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This matches what closed driver does, and avoids problems with CL CTS
allocation tests trying to use too much memory.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:04:30 -08:00
Rob Clark
f5c4dd0d93 freedreno: Use linear for 1d/1d_array
Trying to use UBWC for 1d causes problems with cl cts image writes.  And
also seems kind of pointless.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:04:30 -08:00
Rob Clark
91f5d621f1 freedreno/decode: Add missing a6xx/a7xx reg decoding
Noticed when looking at blob CL traces on a6xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:04:26 -08:00
Rob Clark
2318599252 freedreno/a6xx: Rework flushing events
Adds missing FLUSH_CACHE event, and combines the flushing with existing
barrier emit to avoid duplicating flushes.

Fixes some flakeyness seen with UBWC images on gen8.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:02 -08:00
Rob Clark
2a751765e7 freedreno/a6xx: Don't emit epilogue per-tile
This was intended to run after _all_ tiles.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:02 -08:00
Rob Clark
19a91a6108 freedreno: Reuse last_fence when possible
Avoid creating a dummy batch in the non-TC (async-flush) path, if we can
re-use last_fence.

This avoids extra flushes with rusticl, which is not using TC.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:02 -08:00
Rob Clark
05e19b365f freedreno: Attach fence to last batch
When we have a sequence of batches to flush (ie. some batch, and all
it's dependent batches), attach a fence to the last in sequence.  This
helps avoid fd_context_flush() from creating an empty batch when it
needs to return a fence, but has nothing else left to flush.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:02 -08:00
Rob Clark
75b3f794a0 freedreno/a6xx: Fix num_groups programming
It would matter more if we used CP_RUN_OPENCL, as CP_EXEC_CS programs
these regs from the pm4 pkt payload.  But might as well at least program
correct values.

This at least makes it easier to compare cmdstream to closed cl driver,
which uses CP_RUN_OPENCL.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:02 -08:00
Rob Clark
97ae8a94d3 freedreno: Block rusticl on older gens
Currently pre-a6xx is missing ir3 support for various things that rusticl
requires, leading to segfaults.

For now, block compute-only contexts on older gens.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:01 -08:00
Rob Clark
560a160f05 freedreno: Flip logging to debug
Debug logging should be optimized out in release builds.  Somehow I
didn't notice that this wasn't the case.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:01 -08:00
Rob Clark
55606efdfc freedreno/a6xx: Barrier debug
Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:01 -08:00
Rob Clark
48a82aa1ad freedreno: Fix stdout vs stderr logging
Everything else uses mesa_log*(), which uses stderr.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
2026-03-01 08:00:01 -08:00
Rob Clark
b618b7e725 freedreno: Add missing cl_gl_sharing cap
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Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40140>
2026-03-01 14:34:36 +00:00
Rob Clark
86f952fade freedreno/fdl: Set layer_size in explicit_layout case
For gl/cl interop, we can be importing things with array layout
(2d_array, etc), which need layer_size to be set correctly, matching
the exported resource.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40140>
2026-03-01 14:34:36 +00:00
Christian Gmeiner
87fca4f51e etnaviv: Limit max line width to 1.0 on GPUs needing wide line emulation
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The HW line rasterizer on some Vivante GPUs doesn't produce
spec-conformant results for wide lines. Correct emulation via
triangle expansion is complex and interacts poorly with features
like primitive IDs, shader side effects (SSBOs, atomics), and
varying interpolation.

Rather than carrying fragile emulation, limit the advertised
max line width to 1.0 on affected GPUs. The GLES3 spec only
requires support for width 1.0, so this doesn't affect conformance.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Daniel Lang <dalang@gmx.at>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40006>
2026-03-01 11:34:56 +00:00
Christian Gmeiner
28ae3c0bf0 etnaviv: hwdb: Add WIDELINE_TRIANGLE_EMU cap
Used to tell if the GPU core needs wide line emulation.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Daniel Lang <dalang@gmx.at>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40006>
2026-03-01 11:34:56 +00:00
Dmitry Baryshkov
28f0157250 freedreno/ci: update nightly expectations
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Document nightly changes occuring in 6ea4fe98..c69f7904:
- KHR-GLES2.shaders.aggressive_optimizations.sin_vec3_frag,
  crash, run out of the register space
- dEQP-GLES2.functional.shaders.indexing.matrix_subscript.mat4_static_loop_write_dynamic_loop_read_fragment,
  passes now
- dEQP-GLES2.functional.color_clear.single_rgba,
  new flake

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40142>
2026-03-01 05:11:28 +00:00
Timothy Arceri
6c60f423b3 st/glsl_to_nir: update state var locations earlier
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We need to update the state var locations before the
st_serialize_base_nir() calls otherwise
_mesa_optimize_state_parameters() can alter params such that
variants wont be able to find the correct match when calling
_mesa_lookup_state_param_idx().

Prior to 891d46f5 this worked because after failing to match
we would end up adding additional params back in that we had
just attempted to optimise.

Fixes: a6fcc2835e ("
st/glsl_to_nir: make sure the variant has the correct locations set")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14837

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40133>
2026-02-28 23:56:10 +00:00
Luigi Santivetti
df6d398d45 pco: fix Mesa-CI regression in pco texture packed formats
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Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Fixes: 9caa563bc9 ("pvr, pco: Commonize texture packing code")
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40156>
2026-02-28 20:25:53 +00:00
Alyssa Rosenzweig
e88346330e nir/lower_io: remove incorrect Intel _block cases
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These should be handled like their non-_block counterparts - there is no i/o
index for them.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40096>
2026-02-28 16:32:14 +00:00
Marek Olšák
c20245832d amd: add gfx11 and gfx12 CP packet definitions
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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40084>
2026-02-28 05:23:59 +00:00
Marek Olšák
f22f117d1a amd: add meson variable idep_amd_generated_headers for all generated headers
group all generated header under the same variable

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40084>
2026-02-28 05:23:59 +00:00
Michael Cheng
6e92be2747 anv: Rename instruction_state_pool to shader_heap
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Shaders are allocated from anv_shader_heap, which is backed by the
util_vma_heap. Rename the VA range field to shader_heap to match current
usage and avoid confusion.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40131>
2026-02-27 17:36:41 +00:00
Yiwei Zhang
69734bb903 pan/fb: fix return type for mali_to_glsl_dim
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Fixes: e3dc3dccd6 ("pan/fb: Add a common FB load shader builder")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40110>
2026-02-27 16:50:00 +00:00
Matt Coster
4d42e934ad ci,cirnm: Fix program name in usage example
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Instead of updating the name manually, use the %(prog)s specifier (as
documented at https://docs.python.org/3/library/argparse.html#prog).

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39853>
2026-02-27 15:56:14 +00:00
Mike Blumenkrantz
b8ee6f3d30 radv: fix multiview fast clears
this was only clearing layer0 because it was ignoring the viewmask

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40123>
2026-02-27 15:07:01 +00:00
Samuel Pitoiset
5fa94dba34 radv: only enable DCC/HTILE if it's compressed with SDMA
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It's wrong to enable compression if it's not compressed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40101>
2026-02-27 11:23:48 +00:00
Samuel Pitoiset
3869a6f967 ac/cmdbuf: only set DCC_WRITE_COMPRESS for DCC on SDMA 5+
Compressed HTILE writes aren't supported at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40101>
2026-02-27 11:23:48 +00:00
Benjamin Cheng
2b2b1d405a radeonsi/vcn: Use full pitch for pre-encode input
In 1f83e73145, the pre-encode input picture size was also reduced.
However it was recently discovered that VCN FW uses the input picture
pitch as the pitch for this, which means that previous change broke
pre-encode.

Fixes: 1f83e73145 ("radeonsi/vcn: Reduce allocated size for pre-encode recon pics")
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40125>
2026-02-27 10:27:27 +00:00
Icenowy Zheng
5a497316d4 pvr: only specially handle gfx subcmd for BeginQuery
Among all subcommands, only gfx subcommands are bound to a query pool,
other subcommands seem to need no special handling.

In addition, if a ResetQuery is done before BeginQuery, the last
subcommand will be a event one, which fails the current assert that
assumes it's a gfx one.

Change the assertion of the subcommand being a gfx one to an addition
check of whether the subcommand is a gfx one.

This fixes crash of Vulkan CTS 1.4.5.1 test
dEQP-VK.query_pool.discard.normal.no_depth.none.discard .

Backport-to: 26.0
Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39753>
2026-02-27 17:29:47 +08:00
Radu Costas
9caa563bc9 pvr, pco: Commonize texture packing code
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Format extraction moved to separate function
Removed some magic numbers

Signed-off-by: Radu Costas <radu.costas@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40067>
2026-02-27 09:08:29 +00:00
Samuel Pitoiset
d583339e79 radv/meta: add a single function for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:39 +00:00
Samuel Pitoiset
8d0206c95f radv/meta: simplify creating pipelines for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:39 +00:00
Samuel Pitoiset
009cf9bfa7 radv/meta: pass a resolve mode for fragment color resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:38 +00:00
Samuel Pitoiset
2c5685ed89 radv/meta: inline one function in the fragment resolve path
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:38 +00:00
Samuel Pitoiset
876b204703 radv/meta: use the same shader for color/depth&stencil fragment resolves
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:37 +00:00
Samuel Pitoiset
fd9cbff41a radv/meta: move the barrier for color fragment resolves outside
This barrier is only needed for rendering resolves (ie. not for
vkCmdResolveImage()). Though, these barriers are likely unnecessary
but let's keep them for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40064>
2026-02-27 08:21:37 +00:00