fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 16:08:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/decode: Add missing a6xx/a7xx reg decoding

Browse source 
Noticed when looking at blob CL traces on a6xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40144>
This commit is contained in:
Rob Clark 2026-02-18 12:55:09 -08:00
parent 2318599252
commit 91f5d621f1
2 changed files with 59 additions and 12 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

43
src/freedreno/decode/cffdec.c
View file

@ -770,18 +770,21 @@ static struct {
REG64(SP_PS_BASE, reg_disasm_gpuaddr64),
REG64(SP_CS_BASE, reg_disasm_gpuaddr64),
REG64(SP_VS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_VS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_HS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_HS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_DS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_DS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_GS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_GS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_PS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_PS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_CS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_CS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_VS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_VS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_HS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_HS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_DS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_DS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_GS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_GS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_PS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_PS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_CS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_CS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_GFX_UAV_BASE, reg_dump_uav64),
REG64(SP_CS_UAV_BASE, reg_dump_uav64),
{NULL},
}, reg_a7xx[] = {
@ -792,6 +795,22 @@ static struct {
REG64(SP_PS_BASE, reg_disasm_gpuaddr64),
REG64(SP_CS_BASE, reg_disasm_gpuaddr64),
REG64(SP_VS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_VS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_HS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_HS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_DS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_DS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_GS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_GS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_PS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_PS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_CS_TEXMEMOBJ_BASE, reg_dump_texmemobj64),
REG64(SP_CS_SAMPLER_BASE, reg_dump_sampler64),
REG64(SP_GFX_UAV_BASE, reg_dump_uav64),
REG64(SP_CS_UAV_BASE, reg_dump_uav64),
{NULL},
}, reg_a8xx[] = {
REG64(SP_VS_BASE, reg_disasm_gpuaddr64),

28
src/freedreno/tests/reference/dEQP-VK.ycbcr.plane_view.image_view.g8_b8_r8_3plane_420_unorm_plane_0_fragment-a750.log
View file

@ -1096,7 +1096,35 @@
+ fcfcfcfc SP_REG_PROG_ID_2: { IJ_PERSP_SAMPLE = r63.x | IJ_LINEAR_SAMPLE = r63.x | XYCOORDREGID = r63.x | ZWCOORDREGID = r63.x }
+ 0000fcfc SP_REG_PROG_ID_3: { LINELENGTHREGID = r63.x | FOVEATIONQUALITYREGID = r63.x }
40001ac620 SP_PS_SAMPLER_BASE: 0x40001ac620 base=4000199000, offset=79392, size=131072
{ XY_MAG = A6XX_TEX_NEAREST | XY_MIN = A6XX_TEX_NEAREST | WRAP_S = A6XX_TEX_REPEAT | WRAP_T = A6XX_TEX_REPEAT | WRAP_R = A6XX_TEX_REPEAT | ANISO = A6XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 }
{ COMPARE_FUNC = FUNC_NEVER | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 }
{ REDUCTION_MODE = A6XX_REDUCTION_MODE_AVERAGE | FASTBORDERCOLOR = A6XX_BORDER_COLOR_0_0_0_0 | BCOLOR = 0 }
{ 3 = 0 }
00000040001ac620: 0000: 00000000 00000000 00000000 00000000
{ XY_MAG = A6XX_TEX_NEAREST | XY_MIN = A6XX_TEX_NEAREST | WRAP_S = A6XX_TEX_REPEAT | WRAP_T = A6XX_TEX_REPEAT | WRAP_R = A6XX_TEX_REPEAT | ANISO = A6XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 }
{ COMPARE_FUNC = FUNC_NEVER | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 }
{ REDUCTION_MODE = A6XX_REDUCTION_MODE_AVERAGE | FASTBORDERCOLOR = A6XX_BORDER_COLOR_0_0_0_0 | BCOLOR = 0 }
{ 3 = 0 }
00000040001ac630: 0000: 00000000 00000000 00000000 00000000
{ XY_MAG = A6XX_TEX_NEAREST | XY_MIN = A6XX_TEX_NEAREST | WRAP_S = A6XX_TEX_REPEAT | WRAP_T = A6XX_TEX_REPEAT | WRAP_R = A6XX_TEX_REPEAT | ANISO = A6XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 }
{ COMPARE_FUNC = FUNC_NEVER | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 }
{ REDUCTION_MODE = A6XX_REDUCTION_MODE_AVERAGE | FASTBORDERCOLOR = A6XX_BORDER_COLOR_0_0_0_0 | BCOLOR = 0 }
{ 3 = 0 }
00000040001ac640: 0000: 00000000 00000000 00000000 00000000
{ XY_MAG = A6XX_TEX_NEAREST | XY_MIN = A6XX_TEX_NEAREST | WRAP_S = A6XX_TEX_REPEAT | WRAP_T = A6XX_TEX_REPEAT | WRAP_R = A6XX_TEX_REPEAT | ANISO = A6XX_TEX_ANISO_1 | LOD_BIAS = 0.000000 }
{ COMPARE_FUNC = FUNC_NEVER | MAX_LOD = 0.000000 | MIN_LOD = 0.000000 }
{ REDUCTION_MODE = A6XX_REDUCTION_MODE_AVERAGE | FASTBORDERCOLOR = A6XX_BORDER_COLOR_0_0_0_0 | BCOLOR = 0 }
{ 3 = 0 }
00000040001ac650: 0000: 00000000 00000000 00000000 00000000
40001ac7c0 SP_PS_TEXMEMOBJ_BASE: 0x40001ac7c0 base=4000199000, offset=79808, size=131072
00000040001ac7c0: 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*
00000040001ac800: 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*
00000040001ac840: 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*
00000040001ac880: 0000: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
*
+? 00000000 SP_PS_VGS_CNTL: 0
+? 00000000 SP_PS_OUTPUT_CONST_CNTL: { 0 }
+? 00000000 SP_PS_OUTPUT_CONST_MASK: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }