Commit graph

6321 commits

Author SHA1 Message Date
Caleb Callaway
f64dbfd08a anv: ANV_DEBUG_WAIT_FOR_ATTACH
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35324>
2025-06-06 07:02:07 +00:00
Rohan Garg
248b8cb8c5 anv: drop anv_can_hiz_clear_ds_view in favor of anv_can_hiz_clear_image
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34824>
2025-06-05 20:27:33 +02:00
Rohan Garg
658b89ac86 anv: Support fast-clears in vkCmdClearDepthStencilImage
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: #11897
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34824>
2025-06-05 20:27:30 +02:00
Rohan Garg
db8b07f88d anv: use the float qualifier to denote the right value
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34824>
2025-06-05 20:26:54 +02:00
Lionel Landwerlin
426ddb4fc9 anv: fix pool allocation failure reporting
When resetting the pool, also reset the allocated size so that failure
to allocation correctly reports VK_ERROR_OUT_OF_POOL_MEMORY instead of
VK_ERROR_FRAGMENTED_POOL.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12690
Tested-by: David Gow <david@ingeniumdigital.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35360>
2025-06-05 09:39:07 +00:00
Calder Young
57c5419bbd anv: Support render to aspect other than IMAGE_ASPECT_COLOR_BIT
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On ANV the vkCmdBeginRendering function was hard coded to use
VK_IMAGE_ASPECT_COLOR_BIT for all color attachments, instead of using
the aspect bit specified when the vkImageView was initialized, which
made it impossible for applications to render to views of multi-planar
formats like VK_FORMAT_G8_B8R8_2PLANE_420_UNORM correctly.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13221
Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35340>
2025-06-05 09:22:16 +00:00
Lionel Landwerlin
79498a0849 brw: fix brw_nir_fs_needs_null_rt helper
In 9b42215e0d ("iris: ensure null render target for specific cases") I
wrongly assumed that writing gl_SampleMask would only happen in
multisampled cases.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9b42215e0d ("iris: ensure null render target for specific cases")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13292
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35313>
2025-06-04 10:10:38 +00:00
Lionel Landwerlin
f0e18c475b intel: remove GRL/intel-clc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35227>
2025-05-29 20:17:13 +00:00
Lionel Landwerlin
828173d79a anv: add support for lower_terminate_to_discard workaround
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35111>
2025-05-26 05:52:30 +00:00
Caleb Callaway
e7454f5318 intel/debug: shader dump filter
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v2: Fixes filtering for various brw shader dump logic

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35061>
2025-05-23 19:57:02 +00:00
Lionel Landwerlin
39f55541a3 anv: don't use pipeline layout at descriptor bind
An application is allowed to bind an empty descriptor set in a place
where a pipeline layout has no descriptor set layout. For example :

  pipeline_layout_A :
     set0 : NULL
     set1 : descriptor_set_layout_A

  vkCmdBindDescriptor :
     set0 : descriptor_set_B (with layout bindingCount=0)
     set1 : descriptor_set_C (compatible with descriptor_set_layout_A)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13227
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35125>
2025-05-23 12:56:31 +00:00
Lionel Landwerlin
2418525b2e anv: avoid 64bit atomics emulation on Xe2+
Xe2+ still requires lowering 64bit image load/store to 2x32bit for the
message format. But atomics work without lowering.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34876>
2025-05-23 10:04:29 +00:00
Paulo Zanoni
d77b49eb0a anv/trtt: don't avoid the TR-TT submission when there is stuff to signal
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When an application issues a sparse binding operation, it may be the
case that the state the app is setting is the state that is already
there. In that case, both n_l3l2_binds and n_l1_binds are zero, so the
batch doesn't contain anything and, since 0802bbd486, we just skip
the batch submission and return.

The problem is that skipping the batch submission and returning
ignores the synchronization: there may be syncobjs that we have to
wait and, more importantly, there may be syncobjs that we have to
signal.

This case is exercised by vkd3d-proton's test suite, but I'm not aware
of any other workload that triggers it. This commit only affects
Meteor Lake and older, as TR-TT is only the default behavior for the
platforms running i915.ko.

Testcase: vkd3d-proton/d3d12/test_sparse_buffer_memory_lifetime
Fixes: 0802bbd486 ("anv/trtt: don't submit empty batches when there are no binds to do")
Reviewed-by: Iván Briano <ivan.briano@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35078>
2025-05-23 00:17:18 +00:00
Dylan Baker
51b51eb676 anv: Add comment why we overmap and then unmap a region
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35114>
2025-05-22 21:14:26 +00:00
Dylan Baker
25dd3923dc anv: attempt to make coverity happy
Coverity is upset that we're using `ptr` after we've `munmap`ed up to
the offset of the region, even though we're just moving past the
unmapped region to the still mapped region. Attempt to make it happy by
doing that calculation before unmapping. If it's still mad there's
nothing left we can do.

CID: 1646981
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
CID: 1646956
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35114>
2025-05-22 21:14:26 +00:00
Dylan Baker
ff5cb90880 anv: avoid potential integer overflow
Coverity points out that we're using a 32bit type on the left side here,
so the entire operation is done as 32 bit instead of 64

CID: 1646960
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35114>
2025-05-22 21:14:26 +00:00
Lionel Landwerlin
df15968813 anv/brw: stop turning load_push_constants into load_uniform
Those intrinsics have different semantics in particular with regards
to divergence. Turning one into the other without invalidating the
divergence information breaks NIR validation. But also the conversion
means we get artificially less convergent values in the shaders.

So just handle load_push_constants in the backend and stop changing
things in Anv.

Fixes a bunch of tests in
   dEQP-VK.descriptor_indexing.*
   dEQP-VK.pipeline.*.push_constant.graphics_pipeline.dynamic_index_*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34546>
2025-05-22 07:49:20 +00:00
Lionel Landwerlin
b204153106 anv: add a comment about Wa_14016820455
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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35101>
2025-05-22 07:31:49 +00:00
Iván Briano
815bcda06d anv: enable VK_KHR_fragment_shader_barycentric
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Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34445>
2025-05-20 20:57:59 +00:00
Iván Briano
6268792a29 anv: set HW state for fragment shader barycentric
When the FS requires it, set the VertexAttributeBypass and
LegacyBaryAssignmentDisable bits accordingly.

Also program the provoking vertex to give us the per-vertex attributes
in the order the Vulkan specification dictates, and track its dynamic
value for the FS to pick up constant interpolated inputs correctly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34445>
2025-05-20 20:57:59 +00:00
Iván Briano
8ee14e5291 brw/anv: add provoking vertex to fs_msaa_flags
This will be necessary to select the right value for flat inputs in
fragment shaders when fragment shader barycentrics are in use.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34445>
2025-05-20 20:57:58 +00:00
Aditya Swarup
6528d267ef anv: Disable fast clear when surface width is 16k
HSD 16023071695 description mentions we need to extend
WA_16021232440 to cover the case when surface width is 16k.

BSpec: 57340

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34838>
2025-05-20 10:44:52 -07:00
Tapani Pälli
5828612da2 anv: use internal rt-null-ahs when any_hit is null
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Tested on BMG and PTL using both settings for RT_CTRL.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35044>
2025-05-20 10:58:53 +00:00
Lionel Landwerlin
c570740272 anv: enable preemption setting on command/batch correctly
The 2 helpers we're using for doing internal operations (copies,
command generation, etc...) can work on command buffers or lower level
batches.

When working with command buffers, the helpers should set the
preemption using genX(cmd_buffer_set_preemption) so that whatever
operation comes after toggles the state back to what it needs and we
minimize the toggles.

When working with batchs, the helpers should disable preemption using
genX(batch_set_preemption) and turn it back on when done.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35030>
2025-05-19 06:56:04 +00:00
Jianxun Zhang
2212865ce0 anv: Use different PAT entries for compressed resources
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Displayable compressed resournces have a different PAT
entry from the non-displayable compressed.

Signed-off-by: Jianxun Zhang <jianxun.zhang@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29928>
2025-05-16 16:03:54 -07:00
Kenneth Graunke
20222cd956 anv: Use the new nir_opt_acquire_release_barriers pass
Improves performance of Phasmophobia with the "Eye Adaptation" video
setting enabled on Arc B570 by about 9.5%.

fossil-db results on Battlemage:

   Totals:
   Instrs: 148797922 -> 148797865 (-0.00%)
   Send messages: 7066341 -> 7066317 (-0.00%)
   Cycle count: 21459978352 -> 21459975048 (-0.00%)

   Totals from 8 (0.00% of 574410) affected shaders:
   Instrs: 4633 -> 4576 (-1.23%)
   Send messages: 479 -> 455 (-5.01%)
   Cycle count: 611886 -> 608582 (-0.54%)

Observed to cut 15% of sends in a Phasmophobia shader, 8.3% in a Far Cry
New Dawn shader, 7% in a Borderlands 3 DX11 shader, and 3.4-3.7% of
sends in a few Witcher 3 and Dark Souls 3 shaders.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33504>
2025-05-16 00:29:13 +00:00
José Roberto de Souza
cb6f96a1e8 anv: Remove a '#if GFX_VER >= 30' block inside of a else of '#if GFX_VERx10 >= 125'
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Removing deadcode.

Reviewed-by: Lucas Fryzek <lfryzek@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34988>
2025-05-15 15:25:12 +00:00
José Roberto de Souza
37b42ef648 anv: Drop '#if GFX_VERx10 >= 125' inside of '#if GFX_VERx10 >= 125'
This is just redundant.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34988>
2025-05-15 15:25:12 +00:00
José Roberto de Souza
3cd972a2d3 anv: Enable preemption due 3DPRIMITIVE in GFX 12
The issues preventing it to be enabled were fixed so now we can enable
it but we need also to enable workaround 16013994831 back again.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34988>
2025-05-15 15:25:12 +00:00
José Roberto de Souza
2432d6677e anv: Implement missing part of Wa_1604061319
Description of this workaround are not clear but looking at Iris
implementation we need to emit all 3DSTATE_PUSH_CONSTANT_ALLOC_XS if
any 3DSTATE_PUSH_CONSTANT_ALLOC_XS is emitted.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34988>
2025-05-15 15:25:12 +00:00
Hyunjun Ko
7ddf51dc99 anv: Fix to set CDEF filter flag correctly.
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This fixes to play av1_intel_broken2.ivf.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34866>
2025-05-15 01:02:05 +00:00
Hyunjun Ko
2e256a3cee anv: Allocate MV buffers enough for AV1 decoding.
As other video memories for AV1 are already allocated for the maximum
sizes, now it does the same for MV buffers too.

This fixes a bunch of artifacts of AV1 playing.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34866>
2025-05-15 01:02:05 +00:00
Hyunjun Ko
f4d480f808 anv: Always allocate cdf tables when independent profiles provided
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34866>
2025-05-15 01:02:05 +00:00
Nanley Chery
4502254cd2 anv: Drop the slow clear heuristic
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This no longer provides a performance improvement.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33776>
2025-05-13 15:13:05 +00:00
Nanley Chery
8dad01903a intel: Add and use isl_surf_image_has_unique_tiles()
Returns whether or not a subresource range maps to a tile-aligned memory
range which doesn't overlap other subresources.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33776>
2025-05-13 15:13:04 +00:00
Nanley Chery
fcdae4d4c0 intel: Add and use isl_surf_from_mem()
Unify code which creates surfaces from buffers. The behavior is slightly
changed to use array layers to enable arrayed buffer clears (as needed).

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33776>
2025-05-13 15:13:04 +00:00
Iván Briano
99405647a4 anv: vkCmdTraceRays* are not covered by conditional rendering
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The spec says:
  Certain rendering commands can be executed conditionally based on a
  value in buffer memory. These rendering commands are limited to
  drawing commands, dispatching commands, and clearing attachments with
  vkCmdClearAttachments within a conditional rendering block which is
  defined by commands vkCmdBeginConditionalRenderingEXT and
  vkCmdEndConditionalRenderingEXT. Other rendering commands remain
  unaffected by conditional rendering.

It would seem that vkCmdTraceRays* are not covered by that.

Fixes new tests dEQP-VK.conditional_rendering.conditional_ignore.trace_rays*

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34864>
2025-05-08 21:08:06 +00:00
Lionel Landwerlin
5c7c1eceb5 anv/brw: handle pipeline libraries with mesh
I always thought there was a massive issue with pipeline libraries &
mesh shaders. Indeed recent CTS tests have exposed a number of issues.

Some values delivered to the fragment shader are coming from different
places depending on whether the preceding shader is Mesh or not. For
example PrimitiveID is delivered in the per-primitive block in Mesh
pipelines whereas for other pipelines it's coming as a VUE slot (which
is per-vertex). Those are 2 different locations in the payload.

We have to find a layout for fragment shaders that is compatible with
everything. Leaving gaps here and there in the thread payload.

Fixes the following test pattern :

  dEQP-VK.mesh_shader.ext.smoke.fast_lib.shared_*

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:35 +00:00
Lionel Landwerlin
18bbcf9a63 intel: introduce new VUE layout for separate compiled shader with mesh
Mesh shaders have per vertex block in URB pretty much identical to the
VUE format. Let's just reuse that concept to do all of our layout in
the payload attribute registers. This will ensure that we have
consistent VUE layout between Mesh & non-Mesh pipelines.

We need a new way of laying out the VUE though as we have to
accomodate a HW constraint of maximum (per-primitive + per-vertex) of
32 varying. This means we cannot have 2 locations in the payload for
things like PrimitiveID which can come from either the per-primitive
or the per-vertex block. The new layout places the PrimitiveID at the
end of the per-vertex attributes and shrinks the delivery dynamically
if the mesh stage is active. The shader is compiled with a
MOV_INDIRECT to read the PrimitiveID from the right location in the
attributes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:35 +00:00
Lionel Landwerlin
2d396f6085 intel: prepare VUE layout for more than 2 layouts
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:35 +00:00
Lionel Landwerlin
ef17fbf8e5 anv/brw: use separate_shader to deduced MUE compaction
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:35 +00:00
Lionel Landwerlin
75b2d000fc anv: tidy up (CLIP|SBE)_MESH emission
Moving it to is related functions.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Lionel Landwerlin
62d2e323ba anv/brw: shrink FS varying payload
We're currently allocating payload spots for 3 fields already
delivered somewhere else in the payload.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Lionel Landwerlin
4f10a1f618 anv: switch to brw helpers to figure out if a fragment is dynamic
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Lionel Landwerlin
cb461fa287 anv: switch to use the tcs_prog_data for dynamic input vertices
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Lionel Landwerlin
4717382f84 anv: lower input vertices for TCS unconditionally
Take the opportunity to reuse the backend pass.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Lionel Landwerlin
119ef792c5 anv: remove tbimr workaround check
Already handled by having a special range created

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34109>
2025-05-08 06:48:34 +00:00
Emma Anholt
4cc66123ec anv/ds: Forward VkDebugUtilsObjectNameInfoEXT to perfetto.
This gets us names on zink/wsi command buffers in perfetto, but may also
be useful some day for getting app names onto framebuffers and non-dynamic
renderpasses.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22350>
2025-05-08 01:21:25 +00:00
Emma Anholt
55d788f434 anv/ds: Associate the VkCommandBuffer some anv-only renderstage events.
This means the perfetto UI will have a non-zero/NULL handle/name in the UI
on these renderstages.  Unfortunately, intel/ds is outside of vulkan so
unless we pull in anv headers, we can't just pass in the anv_cmd_buffer.
This also means it would be much more painful to pass the cmd buffer to
the rest of the events, so they'll still have unset command buffers.
Still, being able to see the name of the command buffer in at least one of
the events should be useful once that's glued together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22350>
2025-05-08 01:21:25 +00:00
Sagar Ghuge
bb61a78911 anv: Fix untyped data port cache pipe control dump output
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Fixes: 845ab3d627
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34855>
2025-05-07 19:29:50 +00:00