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brw: fix brw_nir_fs_needs_null_rt helper

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In 9b42215e0d ("iris: ensure null render target for specific cases") I
wrongly assumed that writing gl_SampleMask would only happen in
multisampled cases.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9b42215e0d ("iris: ensure null render target for specific cases")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13292
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35313>
This commit is contained in:
Lionel Landwerlin 2025-06-03 15:41:50 +03:00 • committed by Marge Bot
parent 226b0e28db
commit 79498a0849
3 changed files with 4 additions and 11 deletions
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1
src/gallium/drivers/iris/iris_program.c
View file

@ -2690,7 +2690,6 @@ iris_compile_fs(struct iris_screen *screen,
brw_nir_lower_fs_outputs(nir);
int null_rts = brw_nir_fs_needs_null_rt(devinfo, nir,
key->multisample_fbo,
key->alpha_to_coverage) ? 1 : 0;
struct iris_binding_table bt;

13
src/intel/compiler/brw_nir.h
View file

@ -143,8 +143,7 @@ brw_nir_ubo_surface_index_get_bti(nir_src src)
/* Returns true if a fragment shader needs at least one render target */
static inline bool
brw_nir_fs_needs_null_rt(const struct intel_device_info *devinfo,
nir_shader *nir,
bool multisample_fbo, bool alpha_to_coverage)
nir_shader *nir, bool alpha_to_coverage)
{
assert(nir->info.stage == MESA_SHADER_FRAGMENT);
@ -158,15 +157,11 @@ brw_nir_fs_needs_null_rt(const struct intel_device_info *devinfo,
* output.
*/
if (nir->info.outputs_written & (BITFIELD_BIT(FRAG_RESULT_DEPTH) |
BITFIELD_BIT(FRAG_RESULT_STENCIL)))
BITFIELD_BIT(FRAG_RESULT_STENCIL) |
BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)))
return true;
uint64_t relevant_outputs = 0;
if (multisample_fbo)
relevant_outputs |= BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
return (alpha_to_coverage ||
(nir->info.outputs_written & relevant_outputs) != 0);
return alpha_to_coverage;
}
void brw_preprocess_nir(const struct brw_compiler *compiler,

1
src/intel/vulkan/anv_pipeline.c
View file

@ -1522,7 +1522,6 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
num_rt_bindings = stage->key.wm.nr_color_regions;
} else if (brw_nir_fs_needs_null_rt(
compiler->devinfo, stage->nir,
stage->key.wm.multisample_fbo != INTEL_NEVER,
stage->key.wm.alpha_to_coverage != INTEL_NEVER)) {
/* Ensure the shader doesn't discard the writes */
stage->key.wm.color_outputs_valid = 0x1;