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anv: drop anv_can_hiz_clear_ds_view in favor of anv_can_hiz_clear_image

Browse source 
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34824>
This commit is contained in:
Rohan Garg 2025-06-03 13:44:44 +02:00
parent 658b89ac86
commit 248b8cb8c5
4 changed files with 11 additions and 96 deletions
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12
src/intel/vulkan/anv_blorp.c
View file

@ -2058,12 +2058,12 @@ can_hiz_clear_att(struct anv_cmd_buffer *cmd_buffer,
if (pRects[0].layerCount > 1 || pRects[0].baseArrayLayer > 0)
return false;
return anv_can_hiz_clear_ds_view(cmd_buffer->device, ds_att->iview,
ds_att->layout,
attachment->aspectMask,
attachment->clearValue.depthStencil.depth,
pRects->rect,
cmd_buffer->queue_family->queueFlags);
return anv_can_hiz_clear_image(cmd_buffer, ds_att->iview->image,
ds_att->layout,
attachment->aspectMask,
attachment->clearValue.depthStencil.depth,
pRects->rect,
ds_att->iview->vk.base_mip_level);
}
static void

76
src/intel/vulkan/anv_image_view.c
View file

@ -168,82 +168,6 @@ anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
return util_bitcount(aspect_mask);
}
bool
anv_can_hiz_clear_ds_view(struct anv_device *device,
const struct anv_image_view *iview,
VkImageLayout layout,
VkImageAspectFlags clear_aspects,
float depth_clear_value,
VkRect2D render_area,
const VkQueueFlagBits queue_flags)
{
if (INTEL_DEBUG(DEBUG_NO_FAST_CLEAR))
return false;
/* If we're just clearing stencil, we can always HiZ clear */
if (!(clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
return true;
/* We must have depth in order to have HiZ */
if (!(iview->image->vk.aspects & VK_IMAGE_ASPECT_DEPTH_BIT))
return false;
const enum isl_aux_usage clear_aux_usage =
anv_layout_to_aux_usage(device->info, iview->image,
VK_IMAGE_ASPECT_DEPTH_BIT,
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT,
layout, queue_flags);
if (!isl_aux_usage_has_fast_clears(clear_aux_usage))
return false;
if (isl_aux_usage_has_ccs(clear_aux_usage)) {
/* From the TGL PRM, Vol 9, "Compressed Depth Buffers" (under the
* "Texture performant" and "ZCS" columns):
*
* Update with clear at either 16x8 or 8x4 granularity, based on
* fs_clr or otherwise.
*
* Although alignment requirements are only listed for the texture
* performant mode, test results indicate that requirements exist for
* the non-texture performant mode as well. Disable partial clears.
*/
if (render_area.offset.x > 0 ||
render_area.offset.y > 0 ||
render_area.extent.width !=
u_minify(iview->vk.extent.width, iview->vk.base_mip_level) ||
render_area.extent.height !=
u_minify(iview->vk.extent.height, iview->vk.base_mip_level)) {
return false;
}
/* When fast-clearing, hardware behaves in unexpected ways if the clear
* rectangle, aligned to 16x8, could cover neighboring LODs.
* Fortunately, ISL guarantees that LOD0 will be 8-row aligned and
* LOD0's height seems to not matter. Also, few applications ever clear
* LOD1+. Only allow fast-clearing upper LODs if no overlap can occur.
*/
const struct isl_surf *surf =
&iview->image->planes[0].primary_surface.isl;
assert(isl_surf_usage_is_depth(surf->usage));
assert(surf->dim_layout == ISL_DIM_LAYOUT_GFX4_2D);
assert(surf->array_pitch_el_rows % 8 == 0);
if (clear_aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT &&
iview->vk.base_mip_level >= 1 &&
(iview->vk.extent.width % 32 != 0 ||
surf->image_alignment_el.h % 8 != 0)) {
return false;
}
}
if (device->info->ver <= 12 &&
depth_clear_value != anv_image_hiz_clear_value(iview->image).f32[0])
return false;
/* If we got here, then we can fast clear */
return true;
}
void
anv_image_view_init(struct anv_device *device,
struct anv_image_view *iview,

9
src/intel/vulkan/anv_private.h
View file

@ -6097,15 +6097,6 @@ anv_cmd_flush_buffer_write_cp(VkCommandBuffer cmd_buffer);
VkResult
anv_cmd_buffer_ensure_rcs_companion(struct anv_cmd_buffer *cmd_buffer);
bool
anv_can_hiz_clear_ds_view(struct anv_device *device,
const struct anv_image_view *iview,
VkImageLayout layout,
VkImageAspectFlags clear_aspects,
float depth_clear_value,
VkRect2D render_area,
const VkQueueFlagBits queue_flags);
bool
anv_can_hiz_clear_image(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,

10
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -5681,11 +5681,11 @@ void genX(CmdBeginRendering)(
if (clear_aspects != 0) {
const bool hiz_clear =
anv_can_hiz_clear_ds_view(cmd_buffer->device, d_iview,
depth_layout, clear_aspects,
clear_value.depth,
render_area,
cmd_buffer->queue_family->queueFlags);
anv_can_hiz_clear_image(cmd_buffer, ds_iview->image,
depth_layout, clear_aspects,
clear_value.depth,
render_area,
ds_iview->vk.base_mip_level);
if (depth_layout != initial_depth_layout) {
assert(render_area.offset.x == 0 && render_area.offset.y == 0 &&