Note that what we do is to just return false on the favor/select accum
methods. We could just avoid to call them, but as the select is called
more than once, it is just easier this way.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Note that we provide new v71 alu pack/unpack methods. As there are a
lot that it is equivalent, initially we tried to use existing methods
as template and add version checks on the existing methods. At some
early point that become just really unreadable, so it become better to
just provide new methods, even if v42 and v71 methods have a really
similar structure.
Note that we have splitted the op tables, and created a two (add/mul)
for v71. As the description struct include versioning info, we could
have just used one table. But, specially with the add table, there are
a lot of differences with v71. So it is slightly tidier this
way. Also, taking into account that we do a linear search on the
tables, this can be even justified by performance.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
On v71 rf0 replaces r5 as the register that gets updated implicitly
with uniform loads, and gets the C coefficient with ldvary. This
helper return if rf0 gets implicitly updated.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Even if we can just check for the version on the code, checking for
this field makes several places more readable. So for example, on the
register allocate code we doesn't assign an accumulator because we
don't have accumulators on that hw, instead of because hw version is a
given one.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
On V3D 7.x mux are not used, and raddr_a/b/c/d are used instead
This is not perfect, as for v71, the raddr_a/b defined at qpu_instr
became superfluous. But the alternative would be to define two
different structs, or even having them defined based on version
ifdefs, so this is a reasonable compromise.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
At this point it just tidy up a little the alu_instr structure.
But also serves to prepare the structure for new changes, as 7.x uses
raddr instead of mux, and it is just easier to add the raddr to the
new input structure.
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Compared with v41, the differences are:
* 14, 15, 29 and 30 are now about immediate a, b, c, d respectively
* 23 is now reserved. On v42 this was for rotate signals, that are
gone on v71.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
small_imm_a, small_imm_c and small_imm_d added on top of the already
existing small_imm_b, as V3D 7.1 defines 4 small immediates, tied to
the 4 raddr. Note that this is only the definition, and just a inst
validation rule to check that are not used before v71. Any real use is
still pending.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Current small_imm is associated with the "B" read address.
We do this change in advance for v71 support, where we will have 4
different small_imm (a/b/c/d), so we start with a renaming.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
V3D 7.x got rid of the accumulator, but still uses the values for
WADDR_R5 and WADDR_R5REP, so let's return a proper name and add some
aliases.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
The subrev field from the hub ident3 register is bumped with every
hardware revision doing backwards incompatible changes so we want to
keep track of this.
Instead of modifying the 'ver' field info to acommodate subrev info,
which would require a lot of changes, simply add a new 'rev' field in
devinfo that we can use when we need to make changes based on the
revision number of a hardware release.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Using as reference the spec for 7.1.5. This include totally new
packets, and redefine some that already existed on v42.
Full list:
* Add Depth Bounds Test Limits
* Redefine Tile Binning Mode Cfg
* Redefine Cfg Bits. There are some changes on the fields:
* Line Rasterization is now 1 bit size
* Depth Bounds Enable (that takes one of the bits of Line Rasterization)
* Early-Z/Early-Z updates enable bits (16-17) figure now as reserved.
* New Z-Clipping mode field
* Redefine Tile Rendering Mode Cfg (Common). Changes with respect to v42:
* New log2 tile height/width fields starting at bit 52/55
* Due those two news, end pad is smaller
* sub-id has now a size of 3. Bit 4 is reserved.
* Number of render targets: this field max value is now 7 (not
reflected on the xml).
* Maximum BPP is removed on v71 (now bits 40-41 are reserved)
* Depth Buffer disable: on bit 44
* Update Store Tile Buffer General
* Adding Cfg Render Target Part1/2/3 packets: they replace v4X "Tile
Rendering Mode Cfg (Color)" (real name "Rendering Configuration
(Render Targets Config)"), "Tile Rendering Mode Cfg (Clear Colors
Part1)", "Tile Rendering Mode Cfg (Clear Colors Part2)", and "Tile
Rendering Mode Cfg (Clear Colors Part3)". On those old versions,
the first packet is used to configure 4 render targets. Now that 8
are supported, invididual per-render-target are used.
* Update ZS clear values packet.
* Add new v71 output formats
* Define Clear Render Targets (Replaces Clear Tile Buffers from v42)
* Redefine GL Shader State Record. Changes copared with v42:
* Fields removed:
* "Coordinate shader has separate input and output VPM blocks"
(reserved bit now)
* "Vertex shader has separate input and output VPM blocks"
(reserved bit now)
* "Address of table of default attribute Values." (we needed to
change the start position for all the following fields)
* New field:
* "Never defer FEP depth writes to fragment shader auto Z writes
on scoreboard conflict"
* Redefine clipper xy scaling: Now it uses 1/64ths of pixels, instead
of 1/256ths
* Update texture shader state.
* Notice we don't use an address type for these fields in the XML
description. This is because the addresses are 64-bit aligned
(even though the PRM doesn't say it) which means the 6 LSB bits
are implicitly 0, but the fields are encoded before the 6th bit
of their starting byte, so we can't use the usual trick we do
with address types where the first 6 bits in the byte are
implicitly overwritten by other fields and we have to encode this
manually as a uint field. This would mean that if we had an
actual BO we would also need to add it manually to the job's
list, but since we don't have one, we don't have to do anything
about it.
* Add new RB_Swap field for texture shader state
* Document Cb/Cr addresses as uint fields in texture shader state
* Fixup Blend Config description: we now support 8 RTs.
* TMU config parameter 2 has new fields
* Add new clipper Z without guardband packet in v71
* Add enums for the Z clip modes accepted in v71
* Fix texture state array stride packing for V3D 7.1.5
Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
This register is new in 7.x, it doesn't seem that we need to
do anything specific for now, but let's make sure it is reset
every time.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
This adds 7.1 to the list of available V3D_VERSION, and first changes
on the simulator needed to get it working.
Note that we needed to touch all those 4 codebases because it is
needed if we want to use V3D_DEBUG=clif with the simulator, that it is
the easier way to see which packets a vulkan program is using.
About the simulator, this commit only handle the rename of some
registers. Any additional changes needed to get a proper support for
v71 will be handled them on following commits.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
Use the correct miptail start LOD for the surfaces involved in the
XY_BLOCK_COPY_BLT/XY_FAST_COLOR_BLT instructions.
Thanks to Lionel for pointing out the issue.
Fixes: 46f45d62d1 ("intel/isl: Start using miptails")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25688>
Sometimes, users don't have a recent enough version of wayland-protocols
to build Mesa. But these days, Meson's WrapDB has a wrap that's more
than new enough for our needs.
If we add the wrap-file to the subprojects folder, we'll download a more
recent wrap if the installed version is too old (or doesn't exist at
all).
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25683>
Moving a few functions further up here to prepare for the next commit;
should make the diffs a lot nicer. No (intentional) functional changes.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25326>
in Android 12 build have error "ninja:
'external/mesa/src/compiler/isaspec/README.rst', needed by
'out/target/product/s/obj/MESON_MESA3D_GEN/.timestamp', missing and
no known rule to make it" because commit:
d48d8aefdf (docs: Move isaspec out of
drivers/freedreno) modify isaspec.rst Location.
Signed-off-by: cheyang <cheyang@bytedance.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25697>
OpenCL does not require that a kernel is created for every device. So we
shouldn't assume there is a build for every device.
API validation around launching kernels already takes this possibility
into account.
I did not verify if the commit below is actually the culprit and whether
this bug existed before that, but a fix for older code also would have to
look differently anyway.
Fixes: 323dcbb4b5 ("rusticl: Move NirKernelBuild to ProgramDevBuild")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9968
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25696>
Those workarounds are temporary for newer platforms so we can't use
INTEL_NEEDS_WA_*, luckly those already had runtime checks.
INTEL_NEEDS_WA_* was only used because it was accessing instructions
or fields of the instructions that only exists in gfx12 or gfx125.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25685>
this avoids a number of cases where a shader was reading more components
from an input than an output was providing. functionally there was never
any issue as these read components were subsequently rewritten to use
constant data, but the read itself is a spec violation
shrinking can't be done in finalize, however, as that enables the frontend
to optimize vertex states, which seems like a good thing but ends up being
a bad thing since it may or may not be consistent across frontends and I
don't wanna deal with having to reorder i/o locations in unintuitive ways
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25433>
