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intel: Prepare implementation of Wa_18019816803 and Wa_16013994831 for future platforms

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Those workarounds are temporary for newer platforms so we can't use
INTEL_NEEDS_WA_*, luckly those already had runtime checks.
INTEL_NEEDS_WA_* was only used because it was accessing instructions
or fields of the instructions that only exists in gfx12 or gfx125.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25685>
This commit is contained in:
José Roberto de Souza 2023-10-12 07:20:18 -07:00 • committed by Marge Bot
parent be0ab37bac
commit 07eede0970
4 changed files with 5 additions and 5 deletions
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2
src/gallium/drivers/iris/iris_state.c
View file

@ -6339,7 +6339,7 @@ iris_preemption_streamout_wa(struct iris_context *ice,
struct iris_batch *batch,
bool enable)
{
#if INTEL_NEEDS_WA_16013994831
#if GFX_VERx10 >= 120
if (!intel_needs_workaround(batch->screen->devinfo, 16013994831))
return;

2
src/intel/blorp/blorp_genX_exec.h
View file

@ -1258,7 +1258,7 @@ blorp_emit_depth_stencil_state(struct blorp_batch *batch,
GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &ds);
#if INTEL_NEEDS_WA_18019816803
#if GFX_VERx10 >= 125
/* Check if need PSS Stall sync. */
if (intel_needs_workaround(batch->blorp->compiler->devinfo, 18019816803) &&
batch->flags & BLORP_BATCH_NEED_PSS_STALL_SYNC) {

2
src/intel/vulkan/genX_blorp_exec.c
View file

@ -297,7 +297,7 @@ blorp_exec_on_render(struct blorp_batch *batch,
}
#endif
#if INTEL_NEEDS_WA_18019816803
#if GFX_VERx10 >= 125
/* Check if blorp ds state matches ours. */
if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
bool blorp_ds_state = params->depth.enabled || params->stencil.enabled;

4
src/intel/vulkan/genX_gfx_state.c
View file

@ -653,7 +653,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer)
SET(PMA_FIX, pma_fix, pma);
#endif
#if INTEL_NEEDS_WA_18019816803
#if GFX_VERx10 >= 125
if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
bool ds_write_state = opt_ds.depth.write_enable || opt_ds.stencil.write_enable;
if (cmd_buffer->state.gfx.ds_write_state != ds_write_state) {
@ -1689,7 +1689,7 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer)
}
}
#if INTEL_NEEDS_WA_18019816803
#if GFX_VERx10 >= 125
if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_WA_18019816803)) {
genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info,
ANV_PIPE_PSS_STALL_SYNC_BIT);