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broadcom/compiler: update node/temp translation for v71
As the offset applied needs to take into account if we have accumulators or not. Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25450>
This commit is contained in:
Iago Toral Quiroga
Marge Bot
parent
3b20208f03
commit
63d633ca7a
1 changed files with 34 additions and 34 deletions
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@ -39,30 +39,31 @@
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CLASS_BITS_R5)
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static inline uint32_t
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temp_to_node(uint32_t temp)
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temp_to_node(struct v3d_compile *c, uint32_t temp)
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{
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return temp + ACC_COUNT;
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return temp + (c->devinfo->has_accumulators ? ACC_COUNT : 0);
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}
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static inline uint32_t
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node_to_temp(uint32_t node)
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node_to_temp(struct v3d_compile *c, uint32_t node)
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{
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assert(node >= ACC_COUNT);
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return node - ACC_COUNT;
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assert((c->devinfo->has_accumulators && node >= ACC_COUNT) ||
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(!c->devinfo->has_accumulators && node >= 0));
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return node - (c->devinfo->has_accumulators ? ACC_COUNT : 0);
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}
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static inline uint8_t
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get_temp_class_bits(struct v3d_ra_node_info *nodes,
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get_temp_class_bits(struct v3d_compile *c,
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uint32_t temp)
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{
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return nodes->info[temp_to_node(temp)].class_bits;
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return c->nodes.info[temp_to_node(c, temp)].class_bits;
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}
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static inline void
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set_temp_class_bits(struct v3d_ra_node_info *nodes,
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set_temp_class_bits(struct v3d_compile *c,
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uint32_t temp, uint8_t class_bits)
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{
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nodes->info[temp_to_node(temp)].class_bits = class_bits;
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c->nodes.info[temp_to_node(c, temp)].class_bits = class_bits;
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}
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static struct ra_class *
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@ -84,7 +85,7 @@ static inline struct ra_class *
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choose_reg_class_for_temp(struct v3d_compile *c, uint32_t temp)
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{
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assert(temp < c->num_temps && temp < c->nodes.alloc_count);
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return choose_reg_class(c, get_temp_class_bits(&c->nodes, temp));
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return choose_reg_class(c, get_temp_class_bits(c, temp));
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}
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static inline bool
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@ -313,7 +314,7 @@ v3d_choose_spill_node(struct v3d_compile *c)
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for (unsigned i = 0; i < c->num_temps; i++) {
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if (BITSET_TEST(c->spillable, i)) {
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ra_set_node_spill_cost(c->g, temp_to_node(i),
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ra_set_node_spill_cost(c->g, temp_to_node(c, i),
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spill_costs[i]);
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}
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}
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@ -482,7 +483,7 @@ v3d_emit_spill_tmua(struct v3d_compile *c,
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c->temp_start[i] < ip && c->temp_end[i] >= ip :
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c->temp_start[i] <= ip && c->temp_end[i] > ip;
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if (thrsw_cross) {
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ra_set_node_class(c->g, temp_to_node(i),
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ra_set_node_class(c->g, temp_to_node(c, i),
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choose_reg_class(c, CLASS_BITS_PHYS));
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}
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}
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@ -509,8 +510,7 @@ v3d_emit_tmu_spill(struct v3d_compile *c,
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* same register class bits as the original.
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*/
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if (inst == position) {
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uint8_t class_bits = get_temp_class_bits(&c->nodes,
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inst->dst.index);
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uint8_t class_bits = get_temp_class_bits(c, inst->dst.index);
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inst->dst = vir_get_temp(c);
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add_node(c, inst->dst.index, class_bits);
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} else {
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@ -574,7 +574,7 @@ v3d_spill_reg(struct v3d_compile *c, int *acc_nodes, int spill_temp)
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reconstruct_op = orig_def->qpu.alu.add.op;
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}
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uint32_t spill_node = temp_to_node(spill_temp);
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uint32_t spill_node = temp_to_node(c, spill_temp);
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/* We must disable the ldunif optimization if we are spilling uniforms */
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bool had_disable_ldunif_opt = c->disable_ldunif_opt;
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@ -739,12 +739,12 @@ v3d_spill_reg(struct v3d_compile *c, int *acc_nodes, int spill_temp)
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* update node priorities based one new liveness data.
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*/
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uint32_t sb_temp =c->spill_base.index;
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uint32_t sb_node = temp_to_node(sb_temp);
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uint32_t sb_node = temp_to_node(c, sb_temp);
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for (uint32_t i = 0; i < c->num_temps; i++) {
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if (c->temp_end[i] == -1)
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continue;
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uint32_t node_i = temp_to_node(i);
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uint32_t node_i = temp_to_node(c, i);
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c->nodes.info[node_i].priority =
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c->temp_end[i] - c->temp_start[i];
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@ -752,7 +752,7 @@ v3d_spill_reg(struct v3d_compile *c, int *acc_nodes, int spill_temp)
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j < c->num_temps; j++) {
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if (interferes(c->temp_start[i], c->temp_end[i],
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c->temp_start[j], c->temp_end[j])) {
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uint32_t node_j = temp_to_node(j);
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uint32_t node_j = temp_to_node(c, j);
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ra_add_node_interference(c->g, node_i, node_j);
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}
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}
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@ -958,7 +958,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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for (int i = 0; i < c->num_temps; i++) {
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if (c->temp_start[i] < ip && c->temp_end[i] > ip) {
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ra_add_node_interference(c->g,
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temp_to_node(i),
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temp_to_node(c, i),
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acc_nodes[3]);
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}
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}
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@ -968,7 +968,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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for (int i = 0; i < c->num_temps; i++) {
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if (c->temp_start[i] < ip && c->temp_end[i] > ip) {
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ra_add_node_interference(c->g,
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temp_to_node(i),
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temp_to_node(c, i),
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acc_nodes[4]);
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}
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}
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@ -987,7 +987,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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* decides whether the LDVPM is in or out)
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*/
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assert(inst->dst.file == QFILE_TEMP);
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set_temp_class_bits(&c->nodes, inst->dst.index,
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set_temp_class_bits(c, inst->dst.index,
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CLASS_BITS_PHYS);
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break;
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}
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@ -1002,7 +1002,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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* phys regfile.
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*/
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assert(inst->dst.file == QFILE_TEMP);
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set_temp_class_bits(&c->nodes, inst->dst.index,
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set_temp_class_bits(c, inst->dst.index,
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CLASS_BITS_PHYS);
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break;
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}
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@ -1024,7 +1024,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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*/
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assert(inst->qpu.alu.mul.op == V3D_QPU_M_MOV);
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assert(inst->dst.file == QFILE_TEMP);
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uint32_t node = temp_to_node(inst->dst.index);
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uint32_t node = temp_to_node(c, inst->dst.index);
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ra_set_node_reg(c->g, node,
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PHYS_INDEX + inst->src[0].index);
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break;
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@ -1043,9 +1043,9 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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*/
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if (!inst->qpu.sig.ldunif) {
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uint8_t class_bits =
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get_temp_class_bits(&c->nodes, inst->dst.index) &
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get_temp_class_bits(c, inst->dst.index) &
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~CLASS_BITS_R5;
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set_temp_class_bits(&c->nodes, inst->dst.index,
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set_temp_class_bits(c, inst->dst.index,
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class_bits);
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} else {
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@ -1054,7 +1054,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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* loads interfere with each other.
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*/
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if (c->devinfo->ver < 40) {
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set_temp_class_bits(&c->nodes, inst->dst.index,
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set_temp_class_bits(c, inst->dst.index,
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CLASS_BITS_R5);
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}
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}
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@ -1064,7 +1064,7 @@ update_graph_and_reg_classes_for_inst(struct v3d_compile *c, int *acc_nodes,
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if (inst->qpu.sig.thrsw) {
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for (int i = 0; i < c->num_temps; i++) {
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if (c->temp_start[i] < ip && c->temp_end[i] > ip) {
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set_temp_class_bits(&c->nodes, i,
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set_temp_class_bits(c, i,
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CLASS_BITS_PHYS);
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}
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}
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@ -1125,7 +1125,7 @@ v3d_register_allocate(struct v3d_compile *c)
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c->nodes.info[i].priority = 0;
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c->nodes.info[i].class_bits = 0;
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} else {
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uint32_t t = node_to_temp(i);
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uint32_t t = node_to_temp(c, i);
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c->nodes.info[i].priority =
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c->temp_end[t] - c->temp_start[t];
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c->nodes.info[i].class_bits = CLASS_BITS_ANY;
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@ -1143,7 +1143,7 @@ v3d_register_allocate(struct v3d_compile *c)
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/* Set the register classes for all our temporaries in the graph */
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for (uint32_t i = 0; i < c->num_temps; i++) {
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ra_set_node_class(c->g, temp_to_node(i),
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ra_set_node_class(c->g, temp_to_node(c, i),
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choose_reg_class_for_temp(c, i));
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}
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@ -1153,8 +1153,8 @@ v3d_register_allocate(struct v3d_compile *c)
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if (interferes(c->temp_start[i], c->temp_end[i],
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c->temp_start[j], c->temp_end[j])) {
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ra_add_node_interference(c->g,
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temp_to_node(i),
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temp_to_node(j));
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temp_to_node(c, i),
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temp_to_node(c, j));
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}
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}
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}
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@ -1171,7 +1171,7 @@ v3d_register_allocate(struct v3d_compile *c)
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if (c->spill_size <
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V3D_CHANNELS * sizeof(uint32_t) * force_register_spills) {
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int node = v3d_choose_spill_node(c);
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uint32_t temp = node_to_temp(node);
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uint32_t temp = node_to_temp(c, node);
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if (node != -1) {
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v3d_spill_reg(c, acc_nodes, temp);
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continue;
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@ -1186,7 +1186,7 @@ v3d_register_allocate(struct v3d_compile *c)
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if (node == -1)
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goto spill_fail;
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uint32_t temp = node_to_temp(node);
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uint32_t temp = node_to_temp(c, node);
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enum temp_spill_type spill_type =
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get_spill_type_for_temp(c, temp);
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if (spill_type != SPILL_TYPE_TMU || tmu_spilling_allowed(c)) {
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@ -1201,7 +1201,7 @@ v3d_register_allocate(struct v3d_compile *c)
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/* Allocation was successful, build the 'temp -> reg' map */
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temp_registers = calloc(c->num_temps, sizeof(*temp_registers));
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for (uint32_t i = 0; i < c->num_temps; i++) {
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int ra_reg = ra_get_node_reg(c->g, temp_to_node(i));
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int ra_reg = ra_get_node_reg(c->g, temp_to_node(c, i));
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if (ra_reg < PHYS_INDEX) {
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temp_registers[i].magic = true;
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temp_registers[i].index = (V3D_QPU_WADDR_R0 +
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