This is implemented in common code in d8ef386f98 ("vulkan: add support
for VK_KHR_internally_synchronized_queues").
Passes dEQP-VK.synchronization2.internally_synchronized_queues.*
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41926>
This will be used for CmdDrawByteCountIndirect on v13, which requires
dividing the byte count by the vertex stride to get the number of
vertices in the draw.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
All we really need for udiv32 is a 32x32->64 multiply, but the most
efficient way to implement that is to move the 32-bit reg into a 64-bit
reg anyway. So, I figured it simpler to just have the caller do that
than passing a scratch reg into the helper.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
v13 adds some register add/sub instructions, and I'd like to use
cs_{add,sub}{32,64} for those to match the naming convention for other
reg/reg instructions. So the existing immediate functions are renamed to
cs_add_imm{32,64}, matching the name of the actual instruction.
Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41655>
Not sure if any workload uses this. This mostly allows us to document
the functionality of HSD 22011236099 on gfx20+.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
These platforms don't support CCS on MCS/HIZ/STC. There's nothing we can
do about this. So, stop warning about it.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
This is a preparation for enabling INTEL_DEBUG=mda in Jay. Since we are
changing the passes to use a new macro, go ahead and use new JAY_NIR_*
macros so we don't have to rename them again when their implementation
gets decoupled from BRW.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41897>
The report data requires VkDeviceMemoryReportCallbackDataEXT::heapIndex
instead of memory type index. Meanwhile, turnip only supports a single
tu_memory_heap and doesn't have a type-to-heap mapping. So here we fix
to report constant 0 for heapIndex.
Fixes: 6d69d7e6bf ("tu: Implement VK_EXT_device_memory_report")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41974>
Handle null descriptors by emitting zeroed descriptor state.
When the nullDescriptor feature is enabled, a dedicated null_bo is
allocated. Null image descriptors now pack a TEXTURE_SHADER_STATE whose
base address points to this BO, ensuring that the TMU reads from valid
memory.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40485>
Add `v3d_nir_lower_null_descriptors` NIR pass to bypass operations
if the descriptor size is zero, returning 0 where necessary.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40485>
On Release builds, I get this:
../../src/intel/tools/intel_eu_stall_viewer.cpp: In function ‘int main(int, char**)’:
../../src/intel/tools/intel_eu_stall_viewer.cpp:269:27: warning: ‘stall_csv_filename’ may be used uninitialized [-Wmaybe-uninitialized]
269 | if (!shaders_directory || !stall_csv_filename) {
| ~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~
../../src/intel/tools/intel_eu_stall_viewer.cpp:244:43: note: ‘stall_csv_filename’ was declared here
244 | const char *shaders_directory = NULL, *stall_csv_filename;
We can't expect gcc to understand that it's a required argument.
This "fixes" b795a1a20c ("intel/tools: add eu stall viewer").
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41946>
We found this to be a good balanc in NAK. Instr itself is inlined and
so is the op discriminant but the contents of the op is boxed. This
means we can determine what op something is without chasing a pointer
but still get to mostly copy pointers as we modify instruction lists.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
These are an annoying special case. In order to keep things consistent
and let us pass in None when we don't want any swizzling and ensure that
None both means "Don't swizzle because this instruction can't" and the
identity swizzle, we need to pick a canonical form. We're already using
None for missing values so it makes sense to canonicalize to None.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
While special constants may, in theory, depend on the hardware
generation, we're always guaranteed a free constant zero. It's
convenient to have this at a higher level in the IR. Zeros also
don't count towards FAU and special constant read limits so there's
no real risk in special-casing them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
