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intel/isl: Fix the initial state HiZ state for Xe2+

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HSD 22011236099 actually states that there are no illegal values for HiZ
for partial clear operations. Other operations (e.g., copies) may still
result in corruption without a preceding ambiguate.

Fixes: a13aab1859 ("intel/isl: Update the initial HiZ state for Xe2+")
Related: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40987
Tested-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41712>
This commit is contained in:
Nanley Chery 2026-05-19 08:41:31 -04:00 • committed by Marge Bot
parent 94fc269270
commit ee40162321
1 changed files with 1 additions and 8 deletions
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9
src/intel/isl/isl_aux_info.c
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@ -144,14 +144,7 @@ isl_aux_get_initial_state(const struct intel_device_info *devinfo,
case ISL_AUX_USAGE_HIZ:
case ISL_AUX_USAGE_HIZ_CCS:
case ISL_AUX_USAGE_HIZ_CCS_WT:
if (devinfo->ver >= 20) {
/* According to HSD 22011236099, there are no illegal values for HiZ.
* As neither the main and aux surfaces contain anything of interest,
* treat them as being in sync. This state can avoid the need to
* ambiguate in some cases.
*/
return ISL_AUX_STATE_RESOLVED;
} else if (zeroed && devinfo->ver <= 11) {
if (zeroed && devinfo->ver <= 11) {
/* On ICL and prior, fast-clearing a HiZ block fills it with zeroes.
* On gfx12+, it is filled with a non-zero value.
*/