mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-06-13 13:48:20 +02:00
kraid: Add the start of a v9 encoder
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
0a4cd88f67
commit
348fd5d3e0
4 changed files with 562 additions and 2 deletions
551
src/panfrost/compiler/kraid/encode_v9.rs
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551
src/panfrost/compiler/kraid/encode_v9.rs
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@ -0,0 +1,551 @@
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// Copyright © 2026 Collabora, Ltd.
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// SPDX-License-Identifier: MIT
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use crate::bitview::*;
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use crate::data_type::*;
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use crate::flow::*;
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use crate::ir::*;
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use crate::isa::v9::*;
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use crate::isa::*;
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use crate::ops::*;
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use crate::swizzle::*;
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use rustc_hash::FxHashMap;
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fn encode_src_ref(src: &SrcRef, last_use: bool) -> u8 {
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match src {
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SrcRef::FAU(fau) => match fau.page {
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FAUPage::User => {
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// The top two bits are in the FAU page
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let idx = (fau.idx % 64) as u8;
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(0b10 << 6) | idx
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}
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FAUPage::Special0 | FAUPage::Special1 | FAUPage::Special3 => {
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assert!(fau.idx < 32);
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(0b111 << 5) | (fau.idx as u8)
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}
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FAUPage::SmallConst => {
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assert!(fau.idx < 32);
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(0b110 << 5) | (fau.idx as u8)
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}
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},
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SrcRef::Reg(reg) => {
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assert!(reg.idx < 32);
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((last_use as u8) << 5) | reg.idx
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}
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_ => panic!("SSAValues and Immediates need to be lowered"),
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}
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}
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fn src_fau_page(src: &Src) -> Option<u8> {
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let SrcRef::FAU(fau) = &src.src_ref else {
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return None;
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};
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match fau.page {
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FAUPage::User => {
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let page = fau.idx / 64;
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assert!(page < 4);
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Some(page as u8)
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}
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FAUPage::Special0 => Some(0),
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FAUPage::Special1 => Some(1),
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FAUPage::Special3 => Some(3),
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FAUPage::SmallConst => None,
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}
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}
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fn op_encode_src(op: &impl Opcode, src: &Src) -> v9::EncodedSrc {
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let encoded = encode_src_ref(&src.src_ref, src.last_use);
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let src_type = op.src_type(src);
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if src_type.bits().unwrap().get() == 64 && !src.src_ref.is_small_const() {
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assert_eq!(encoded & 0x01, 0);
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}
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let swizzle_widen = AsmSwizzleWiden::from_swizzle(src_type, src.swizzle)
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.expect("Invalid swizzle");
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// Sanity check our source modifiers first
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match src.src_mod {
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SrcMod::None => (),
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SrcMod::FAbs | SrcMod::FNeg | SrcMod::FNegAbs => {
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assert_eq!(src_type.num_type(), Some(NumericType::Float));
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}
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SrcMod::BNot => {
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assert_eq!(src_type.num_type(), Some(NumericType::Integer));
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}
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}
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v9::EncodedSrc {
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encoded,
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swizzle: swizzle_widen.into(),
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abs: matches!(src.src_mod, SrcMod::FAbs | SrcMod::FNegAbs),
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neg: matches!(src.src_mod, SrcMod::FNeg | SrcMod::FNegAbs),
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not: matches!(src.src_mod, SrcMod::BNot),
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}
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}
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fn op_encode_dst(op: &impl Opcode, dst: &Dst) -> v9::EncodedDst {
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let Dst::Reg(reg) = dst else {
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panic!("Destination must be a register");
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};
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let dst_type = op.dst_type(dst);
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if dst_type.bits().unwrap().get() == 64 {
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assert_eq!(reg.idx & 0x01, 0);
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}
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let lanes = match reg.range {
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RegRange::Half0 => DstLanes::H0,
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RegRange::Half1 => DstLanes::H1,
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RegRange::Regs(_) => DstLanes::None,
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};
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v9::EncodedDst {
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reg: reg.idx,
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lanes,
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}
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}
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fn op_encode_sr_read(op: &impl Opcode, src: &Src) -> v9::SrRead {
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let SrcRef::Reg(reg) = &src.src_ref else {
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panic!("Staging registers be registers");
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};
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let src_type = op.src_type(src);
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let swizzle = AsmSwizzleWiden::from_swizzle(src_type, src.swizzle)
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.expect("Invalid swizzle");
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let swizzle = swizzle.into();
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assert!(src.src_mod == SrcMod::None);
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let index = reg.idx;
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let count = reg.bytes().div_ceil(4);
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assert_eq!(index % count.next_power_of_two(), 0);
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v9::SrRead {
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index,
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count,
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swizzle,
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}
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}
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fn op_encode_sr_write(op: &impl Opcode, dst: &Dst) -> v9::SrWrite {
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let Dst::Reg(reg) = dst else {
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panic!("Staging registers be registers");
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};
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let reg_bytes = reg.bytes();
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let reg_byte_offset = reg.byte_offset();
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let type_bits = op.dst_type(dst).total_bits().unwrap().get();
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let lanes = if type_bits == 8 {
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match reg_byte_offset {
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0 => DstLanes::B0,
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1 => DstLanes::B1,
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2 => DstLanes::B2,
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3 => DstLanes::B3,
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b => panic!("Invalid byte offset: {b}"),
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}
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} else if type_bits == 16 {
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assert!(reg_bytes >= 2);
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match reg_byte_offset {
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0 => DstLanes::H0,
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2 => DstLanes::H1,
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b => panic!("Invalid byte offset: {b}"),
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}
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} else {
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assert!(reg_bytes * 8 >= type_bits);
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assert_eq!(reg_byte_offset, 0);
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DstLanes::None
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};
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let index = reg.idx;
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let count = reg_bytes.div_ceil(4);
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v9::SrWrite {
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index,
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count,
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lanes,
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}
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}
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fn instr_fau_page(instr: &Instr) -> Option<u8> {
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let mut page = None;
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for src in instr.srcs() {
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let Some(p) = src_fau_page(src) else {
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continue;
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};
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let page = page.get_or_insert(p);
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assert!(*page == p);
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}
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page
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}
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fn encode_flow(mut flow: FlowCtrl, arch: u8) -> FlowControlM {
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if flow.take_end_shader() {
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assert!(flow == FlowCtrl::NONE);
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return FlowControlM::End;
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}
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if flow.take_discard() {
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assert!(flow == FlowCtrl::NONE);
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return FlowControlM::Discard;
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}
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if flow.take_wait_bit(FlowWaitBit::Barrier) {
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return FlowControlM::Wait;
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}
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if arch >= 10 && flow.take_wait_bit(FlowWaitBit::Resource) {
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if flow == FlowCtrl::NONE {
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return FlowControlM::WaitResource;
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} else {
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return FlowControlM::Wait;
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}
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}
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if flow.take_reconverge() {
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if flow == FlowCtrl::NONE {
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return FlowControlM::Reconverge;
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} else {
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return FlowControlM::Wait;
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}
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}
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if flow.take_wait_bit(FlowWaitBit::ZS) {
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if (flow.wait & !0b111) == 0 {
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return FlowControlM::Wait0126;
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} else {
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return FlowControlM::Wait;
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}
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}
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assert!(flow.wait <= 0b111);
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unsafe { std::mem::transmute(flow.wait) }
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}
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impl From<AsmSwizzleWiden> for SrcSwizzle {
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fn from(swizzle: AsmSwizzleWiden) -> SrcSwizzle {
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match swizzle {
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AsmSwizzleWiden::B0 => SrcSwizzle::B0,
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AsmSwizzleWiden::B00 => SrcSwizzle::B00,
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AsmSwizzleWiden::B0000 => SrcSwizzle::B0000,
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AsmSwizzleWiden::B0011 => SrcSwizzle::B0011,
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AsmSwizzleWiden::B01 => SrcSwizzle::B01,
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AsmSwizzleWiden::B0101 => SrcSwizzle::B0101,
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AsmSwizzleWiden::B0123 => SrcSwizzle::B0123,
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AsmSwizzleWiden::B02 => SrcSwizzle::B02,
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AsmSwizzleWiden::B03 => SrcSwizzle::B03,
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AsmSwizzleWiden::B1 => SrcSwizzle::B1,
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AsmSwizzleWiden::B10 => SrcSwizzle::B10,
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AsmSwizzleWiden::B1032 => SrcSwizzle::B1032,
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AsmSwizzleWiden::B11 => SrcSwizzle::B11,
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AsmSwizzleWiden::B1111 => SrcSwizzle::B1111,
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AsmSwizzleWiden::B12 => SrcSwizzle::B12,
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AsmSwizzleWiden::B13 => SrcSwizzle::B13,
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AsmSwizzleWiden::B2 => SrcSwizzle::B2,
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AsmSwizzleWiden::B20 => SrcSwizzle::B20,
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AsmSwizzleWiden::B21 => SrcSwizzle::B21,
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AsmSwizzleWiden::B22 => SrcSwizzle::B22,
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AsmSwizzleWiden::B2222 => SrcSwizzle::B2222,
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AsmSwizzleWiden::B2233 => SrcSwizzle::B2233,
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AsmSwizzleWiden::B23 => SrcSwizzle::B23,
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AsmSwizzleWiden::B2301 => SrcSwizzle::B2301,
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AsmSwizzleWiden::B2323 => SrcSwizzle::B2323,
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AsmSwizzleWiden::B3 => SrcSwizzle::B3,
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AsmSwizzleWiden::B30 => SrcSwizzle::B30,
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AsmSwizzleWiden::B31 => SrcSwizzle::B31,
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AsmSwizzleWiden::B32 => SrcSwizzle::B32,
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AsmSwizzleWiden::B3210 => SrcSwizzle::B3210,
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AsmSwizzleWiden::B33 => SrcSwizzle::B33,
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AsmSwizzleWiden::B3333 => SrcSwizzle::B3333,
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AsmSwizzleWiden::H0 => SrcSwizzle::H0,
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AsmSwizzleWiden::H00 => SrcSwizzle::H00,
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AsmSwizzleWiden::H01 => SrcSwizzle::H01,
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AsmSwizzleWiden::H1 => SrcSwizzle::H1,
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AsmSwizzleWiden::H10 => SrcSwizzle::H10,
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AsmSwizzleWiden::H11 => SrcSwizzle::H11,
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AsmSwizzleWiden::None => SrcSwizzle::None,
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AsmSwizzleWiden::W0 => SrcSwizzle::W0,
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AsmSwizzleWiden::W1 => SrcSwizzle::W1,
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}
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}
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}
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impl From<MemAccess> for AccessLoadM {
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fn from(access: MemAccess) -> AccessLoadM {
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match access {
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MemAccess::None => AccessLoadM::None,
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MemAccess::Istream => AccessLoadM::Istream,
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MemAccess::Estream => AccessLoadM::Estream,
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MemAccess::Force => AccessLoadM::Force,
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}
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}
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}
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impl From<MemAccess> for AccessStoreM {
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fn from(access: MemAccess) -> AccessStoreM {
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match access {
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MemAccess::None => AccessStoreM::None,
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MemAccess::Istream => AccessStoreM::Istream,
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MemAccess::Estream => AccessStoreM::Estream,
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MemAccess::Force => AccessStoreM::Force,
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}
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}
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}
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struct InstrEnc {
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arch: u8,
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fau_page_index: u8,
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flow: FlowControlM,
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}
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impl InstrEnc {
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fn encode(
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self,
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instr: impl TryEncode<Encoded = [u32; 2], Error: std::fmt::Debug>,
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) -> [u32; 2] {
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let mut bits = instr
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.try_encode(self.arch)
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.expect("Failed to encode instruction");
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let flow = self
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.flow
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.try_encode(self.arch)
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.expect("Failed to encode flow");
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let mut b = BitMutView::new(&mut bits);
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b.set_field(57..59, self.fau_page_index);
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b.set_field(59..63, flow);
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bits
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}
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}
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fn encode_instr(
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ip: i64,
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instr: &Instr,
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arch: u8,
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labels: &FxHashMap<Label, i64>,
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) -> [u32; 2] {
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let msg_slot_idx = instr.flow.get_msg_slot_idx().map(|idx| match idx {
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0 => MessageSlotIndexM::Slot0,
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1 => MessageSlotIndexM::Slot1,
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2 => MessageSlotIndexM::Slot2,
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_ => panic!("Invalid message slot"),
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});
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let enc = InstrEnc {
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arch,
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fau_page_index: instr_fau_page(instr).unwrap_or(0),
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flow: encode_flow(instr.flow, arch),
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};
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match &instr.op {
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Op::Branch(op) => enc.encode(Branch {
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not: op.not.into(),
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src0: op_encode_src(op, &op.cond),
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combine: match op.combine_op {
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BranchCombineOp::None => BranchCombineM::And,
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BranchCombineOp::H0 => BranchCombineM::H0,
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BranchCombineOp::H1 => BranchCombineM::H1,
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BranchCombineOp::And => BranchCombineM::Lowbits,
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BranchCombineOp::LowBits => BranchCombineM::None,
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},
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conservative: false.into(),
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offset: labels.get(&op.label).unwrap() - (ip + INSTR_SIZE),
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}),
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Op::FAdd(op) => {
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if let SrcRef::Imm32(imm) = &op.srcs[1].src_ref {
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enc.encode(FaddImm {
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variant: match op.dst_type {
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DataType::F32 => FaddImmVariant::F32,
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DataType::V2F16 => FaddImmVariant::V2f16,
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t => panic!("FADD_IMM.{t} not supported"),
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},
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dst: op_encode_dst(op, &op.dst),
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src0: op_encode_src(op, &op.srcs[0]),
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imm1w: *imm,
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})
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} else {
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enc.encode(Fadd {
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variant: match op.dst_type {
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DataType::F32 => FaddVariant::F32,
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DataType::V2F16 => FaddVariant::V2f16,
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t => panic!("FADD.{t} not supported"),
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},
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dst: op_encode_dst(op, &op.dst),
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src0: op_encode_src(op, &op.srcs[0]),
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src1: op_encode_src(op, &op.srcs[1]),
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clamp: ClampM::None,
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round: Round::None,
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sticky: false.into(),
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})
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}
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}
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Op::FCmp(op) => enc.encode(Fcmp {
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variant: match op.src_type {
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DataType::F32 => FcmpVariant::F32,
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DataType::V2F16 => FcmpVariant::V2f16,
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t => panic!("FCMP.{t} not supported"),
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},
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dst: op_encode_dst(op, &op.dst),
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src0: op_encode_src(op, &op.srcs[0]),
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src1: op_encode_src(op, &op.srcs[1]),
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cmpf: match op.cmp_op {
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CmpOp::Eq => CmpfM::Eq,
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CmpOp::Gt => CmpfM::Gt,
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CmpOp::Ge => CmpfM::Ge,
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CmpOp::Ne => CmpfM::Ne,
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CmpOp::Lt => CmpfM::Lt,
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CmpOp::Le => CmpfM::Le,
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CmpOp::GtLt => CmpfM::Gtlt,
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CmpOp::Total => CmpfM::Total,
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},
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result_type: CmpResultTypeM::M1,
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}),
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Op::IAdd(op) => {
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if let SrcRef::Imm32(imm) = &op.srcs[1].src_ref {
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enc.encode(IaddImm {
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variant: match op.dst_type {
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DataType::I32 => IaddImmVariant::I32,
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DataType::V2I16 => IaddImmVariant::V2i16,
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DataType::V4I8 => IaddImmVariant::V4i8,
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t => panic!("IADD_IMM.{t} not supported"),
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},
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dst: op_encode_dst(op, &op.dst),
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src0: op_encode_src(op, &op.srcs[0]),
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imm1w: *imm,
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})
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} else {
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enc.encode(Iadd {
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variant: match op.dst_type {
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DataType::S32 => IaddVariant::S32,
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DataType::S64 => IaddVariant::S64,
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DataType::U32 => IaddVariant::U32,
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DataType::U64 => IaddVariant::U64,
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DataType::V2S16 => IaddVariant::V2s16,
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DataType::V2U16 => IaddVariant::V2u16,
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DataType::V4S8 => IaddVariant::V4s8,
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DataType::V4U8 => IaddVariant::V4u8,
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t => panic!("IADD.{t} not supported"),
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},
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dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
src1: op_encode_src(op, &op.srcs[1]),
|
||||
saturate: op.saturate.into(),
|
||||
})
|
||||
}
|
||||
}
|
||||
Op::LdPka(op) => enc.encode(LdPka {
|
||||
variant: match op.dst_type {
|
||||
DataType::I8 => LdPkaVariant::I8,
|
||||
DataType::I16 => LdPkaVariant::I16,
|
||||
DataType::I24 => LdPkaVariant::I24,
|
||||
DataType::I32 => LdPkaVariant::I32,
|
||||
DataType::I48 => LdPkaVariant::I48,
|
||||
DataType::I64 => LdPkaVariant::I64,
|
||||
DataType::I96 => LdPkaVariant::I96,
|
||||
DataType::I128 => LdPkaVariant::I128,
|
||||
t => panic!("LD_PKA.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
extend: SignExtendOrNoneM::None,
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.offset),
|
||||
src1: op_encode_src(op, &op.handle),
|
||||
}),
|
||||
Op::LeaPka(op) => enc.encode(LeaPka {
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.offset),
|
||||
src1: op_encode_src(op, &op.handle),
|
||||
}),
|
||||
Op::Load(op) => enc.encode(Load {
|
||||
variant: match op.dst_type {
|
||||
DataType::I8 => LoadVariant::I8,
|
||||
DataType::I16 => LoadVariant::I16,
|
||||
DataType::I24 => LoadVariant::I24,
|
||||
DataType::I32 => LoadVariant::I32,
|
||||
DataType::I48 => LoadVariant::I48,
|
||||
DataType::I64 => LoadVariant::I64,
|
||||
DataType::I96 => LoadVariant::I96,
|
||||
DataType::I128 => LoadVariant::I128,
|
||||
t => panic!("LOAD.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
extend: SignExtendOrNoneM::None,
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.addr),
|
||||
offset: op.offset,
|
||||
}),
|
||||
Op::Mov(op) => {
|
||||
if let SrcRef::Imm32(imm) = &op.src.src_ref {
|
||||
enc.encode(MovImm {
|
||||
variant: match op.dst_type {
|
||||
DataType::I16 => MovImmVariant::V2i16,
|
||||
DataType::I32 => MovImmVariant::I32,
|
||||
t => panic!("MOV_IMM.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
imm1w: *imm,
|
||||
})
|
||||
} else {
|
||||
enc.encode(Mov {
|
||||
variant: match op.dst_type {
|
||||
DataType::I32 => MovVariant::I32,
|
||||
t => panic!("MOV.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.src),
|
||||
})
|
||||
}
|
||||
}
|
||||
Op::Nop(_) => enc.encode(Nop {}),
|
||||
Op::Store(op) => enc.encode(Store {
|
||||
variant: match op.src_type {
|
||||
DataType::I8 => StoreVariant::I8,
|
||||
DataType::I16 => StoreVariant::I16,
|
||||
DataType::I24 => StoreVariant::I24,
|
||||
DataType::I32 => StoreVariant::I32,
|
||||
DataType::I48 => StoreVariant::I48,
|
||||
DataType::I64 => StoreVariant::I64,
|
||||
DataType::I96 => StoreVariant::I96,
|
||||
DataType::I128 => StoreVariant::I128,
|
||||
t => panic!("LOAD.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_src: op_encode_sr_read(op, &op.data),
|
||||
src0: op_encode_src(op, &op.addr),
|
||||
offset: op.offset,
|
||||
}),
|
||||
op => panic!("Instruction not encoded: {op}"),
|
||||
}
|
||||
}
|
||||
|
||||
const INSTR_SIZE: i64 = size_of::<<Mov as TryEncode>::Encoded>() as i64;
|
||||
|
||||
pub fn encode_v9(s: &Shader<'_>, arch: u8) -> Vec<u32> {
|
||||
let mut labels = FxHashMap::default();
|
||||
let mut ip = 0_i64;
|
||||
for b in &s.blocks {
|
||||
labels.insert(b.label, ip);
|
||||
ip += i64::try_from(b.instrs.len()).unwrap() * INSTR_SIZE;
|
||||
}
|
||||
|
||||
let mut enc = Vec::new();
|
||||
let mut ip = 0_i64;
|
||||
for b in &s.blocks {
|
||||
for i in &b.instrs {
|
||||
enc.extend(encode_instr(ip, i, arch, &labels));
|
||||
ip += INSTR_SIZE;
|
||||
}
|
||||
}
|
||||
enc
|
||||
}
|
||||
|
|
@ -120,6 +120,13 @@ impl RegRef {
|
|||
RegRange::Regs(n) => n * 4,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn byte_offset(&self) -> u8 {
|
||||
match self.range {
|
||||
RegRange::Half0 | RegRange::Regs(_) => 0,
|
||||
RegRange::Half1 => 2,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone)]
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ mod bitview;
|
|||
mod builder;
|
||||
mod compile;
|
||||
mod data_type;
|
||||
mod encode_v9;
|
||||
mod flow;
|
||||
mod ir;
|
||||
mod isa;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
// Copyright © 2026 Collabora, Ltd.
|
||||
// SPDX-License-Identifier: MIT
|
||||
|
||||
use crate::encode_v9::*;
|
||||
use crate::ir::*;
|
||||
use kraid_bindings::*;
|
||||
|
||||
|
|
@ -19,8 +20,8 @@ impl Model for ValhallModel {
|
|||
self.arch
|
||||
}
|
||||
|
||||
fn encode_shader(&self, _s: &Shader<'_>) -> Vec<u32> {
|
||||
todo!("Implement Valhall shader encoding");
|
||||
fn encode_shader(&self, s: &Shader<'_>) -> Vec<u32> {
|
||||
encode_v9(s, self.arch)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue