mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-06-09 23:08:18 +02:00
kraid: Break v9 instruction encoding out into traits
This is modeled, again, after what we're doing in NAK. The new traits also allow us to query instruction info from the ISA XML. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41841>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
afb7fb0287
commit
e644edab7a
1 changed files with 516 additions and 265 deletions
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@ -13,6 +13,56 @@ use crate::swizzle::*;
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use paste::paste;
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use rustc_hash::FxHashMap;
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type EncodedInstr = [u32; 2];
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const INSTR_SIZE: i64 = size_of::<EncodedInstr>() as i64;
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trait V9Instr {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo>;
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fn encode(&self, encoder: V9Encoder<'_>) -> EncodedInstr;
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}
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struct V9Encoder<'a> {
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ip: i64,
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instr: &'a Instr,
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arch: u8,
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labels: &'a FxHashMap<Label, i64>,
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}
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impl V9Encoder<'_> {
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fn encode(
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&self,
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isa_instr: impl TryEncode<Encoded = [u32; 2], Error: std::fmt::Debug>,
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) -> [u32; 2] {
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let fau_page_index = instr_fau_page(&self.instr).unwrap_or(0);
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let flow = encode_flow(self.instr.flow, self.arch)
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.try_encode(self.arch)
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.expect("Failed to encode flow");
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let mut bits = isa_instr
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.try_encode(self.arch)
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.expect("Failed to encode instruction");
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let mut b = BitMutView::new(&mut bits);
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b.set_field(57..59, fau_page_index);
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b.set_field(59..63, flow);
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bits
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}
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fn get_msg_slot_idx(&self) -> Option<MessageSlotIndexM> {
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self.instr.flow.get_msg_slot_idx().map(|idx| match idx {
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0 => MessageSlotIndexM::Slot0,
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1 => MessageSlotIndexM::Slot1,
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2 => MessageSlotIndexM::Slot2,
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_ => panic!("Invalid message slot index"),
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})
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}
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fn get_pc_rel_offset(&self, label: &Label) -> i64 {
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self.labels.get(label).unwrap() - (self.ip + INSTR_SIZE)
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}
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}
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fn encode_src_ref(src: &SrcRef, last_use: bool) -> u8 {
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match src {
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SrcRef::FAU(fau) => match fau.page {
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@ -299,6 +349,371 @@ impl From<MemAccess> for AccessStoreM {
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}
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}
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impl V9Instr for OpBranch {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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Branch::get_info((), arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(Branch {
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not: self.not.into(),
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src0: op_encode_src(self, &self.cond),
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combine: match self.combine_op {
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BranchCombineOp::None => BranchCombineM::And,
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BranchCombineOp::H0 => BranchCombineM::H0,
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BranchCombineOp::H1 => BranchCombineM::H1,
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BranchCombineOp::And => BranchCombineM::Lowbits,
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BranchCombineOp::LowBits => BranchCombineM::None,
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},
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conservative: false.into(),
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offset: e.get_pc_rel_offset(&self.label),
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})
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}
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}
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impl V9Instr for OpFAdd {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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if let SrcRef::Imm32(_) = &self.srcs[1].src_ref {
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let variant = match self.dst_type {
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DataType::F32 => FaddImmVariant::F32,
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DataType::V2F16 => FaddImmVariant::V2f16,
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_ => return None,
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};
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FaddImm::get_info(variant, arch)
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} else {
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let variant = match self.dst_type {
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DataType::F32 => FaddVariant::F32,
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DataType::V2F16 => FaddVariant::V2f16,
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_ => return None,
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};
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Fadd::get_info(variant, arch)
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}
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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if let SrcRef::Imm32(imm) = &self.srcs[1].src_ref {
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e.encode(FaddImm {
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variant: match self.dst_type {
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DataType::F32 => FaddImmVariant::F32,
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DataType::V2F16 => FaddImmVariant::V2f16,
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t => panic!("FADD_IMM.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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imm1w: *imm,
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})
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} else {
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e.encode(Fadd {
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variant: match self.dst_type {
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DataType::F32 => FaddVariant::F32,
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DataType::V2F16 => FaddVariant::V2f16,
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t => panic!("FADD.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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src1: op_encode_src(self, &self.srcs[1]),
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clamp: ClampM::None,
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round: Round::None,
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sticky: false.into(),
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})
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}
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}
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}
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impl V9Instr for OpFCmp {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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let variant = match self.src_type {
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DataType::F32 => FcmpVariant::F32,
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DataType::V2F16 => FcmpVariant::V2f16,
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_ => return None,
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};
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Fcmp::get_info(variant, arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(Fcmp {
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variant: match self.src_type {
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DataType::F32 => FcmpVariant::F32,
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DataType::V2F16 => FcmpVariant::V2f16,
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t => panic!("FCMP.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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src1: op_encode_src(self, &self.srcs[1]),
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cmpf: match self.cmp_op {
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CmpOp::Eq => CmpfM::Eq,
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CmpOp::Gt => CmpfM::Gt,
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CmpOp::Ge => CmpfM::Ge,
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CmpOp::Ne => CmpfM::Ne,
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CmpOp::Lt => CmpfM::Lt,
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CmpOp::Le => CmpfM::Le,
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CmpOp::GtLt => CmpfM::Gtlt,
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CmpOp::Total => CmpfM::Total,
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},
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result_type: CmpResultTypeM::M1,
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})
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}
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}
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impl V9Instr for OpIAdd {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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if let SrcRef::Imm32(_) = &self.srcs[1].src_ref {
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let variant = match self.dst_type {
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DataType::I32 => IaddImmVariant::I32,
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DataType::V2I16 => IaddImmVariant::V2i16,
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DataType::V4I8 => IaddImmVariant::V4i8,
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_ => return None,
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};
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IaddImm::get_info(variant, arch)
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} else {
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let variant = match self.dst_type {
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DataType::S32 => IaddVariant::S32,
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DataType::S64 => IaddVariant::S64,
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DataType::U32 => IaddVariant::U32,
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DataType::U64 => IaddVariant::U64,
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DataType::V2S16 => IaddVariant::V2s16,
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DataType::V2U16 => IaddVariant::V2u16,
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DataType::V4S8 => IaddVariant::V4s8,
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DataType::V4U8 => IaddVariant::V4u8,
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_ => return None,
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};
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Iadd::get_info(variant, arch)
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}
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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if let SrcRef::Imm32(imm) = &self.srcs[1].src_ref {
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e.encode(IaddImm {
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variant: match self.dst_type {
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DataType::I32 => IaddImmVariant::I32,
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DataType::V2I16 => IaddImmVariant::V2i16,
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DataType::V4I8 => IaddImmVariant::V4i8,
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t => panic!("IADD_IMM.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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imm1w: *imm,
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})
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} else {
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e.encode(Iadd {
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variant: match self.dst_type {
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DataType::S32 => IaddVariant::S32,
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DataType::S64 => IaddVariant::S64,
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DataType::U32 => IaddVariant::U32,
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DataType::U64 => IaddVariant::U64,
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DataType::V2S16 => IaddVariant::V2s16,
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DataType::V2U16 => IaddVariant::V2u16,
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DataType::V4S8 => IaddVariant::V4s8,
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DataType::V4U8 => IaddVariant::V4u8,
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t => panic!("IADD.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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src1: op_encode_src(self, &self.srcs[1]),
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saturate: self.saturate.into(),
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})
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}
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}
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}
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impl V9Instr for OpICmp {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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let variant = match self.src_type {
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DataType::S32 => IcmpVariant::S32,
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DataType::U32 => IcmpVariant::U32,
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DataType::V2S16 => IcmpVariant::V2s16,
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DataType::V2U16 => IcmpVariant::V2u16,
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_ => return None,
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};
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Icmp::get_info(variant, arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(Icmp {
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variant: match self.src_type {
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DataType::S32 => IcmpVariant::S32,
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DataType::U32 => IcmpVariant::U32,
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DataType::V2S16 => IcmpVariant::V2s16,
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DataType::V2U16 => IcmpVariant::V2u16,
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t => panic!("FCMP.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.srcs[0]),
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src1: op_encode_src(self, &self.srcs[1]),
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cmpf: match self.cmp_op {
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CmpOp::Eq => CmpfM::Eq,
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CmpOp::Gt => CmpfM::Gt,
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CmpOp::Ge => CmpfM::Ge,
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CmpOp::Ne => CmpfM::Ne,
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CmpOp::Lt => CmpfM::Lt,
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CmpOp::Le => CmpfM::Le,
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cmp_op => panic!("Unsupported comparison: {cmp_op}"),
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},
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result_type: CmpResultTypeM::M1,
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})
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}
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}
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impl V9Instr for OpLdPka {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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let variant = match self.dst_type {
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DataType::I8 => LdPkaVariant::I8,
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DataType::I16 => LdPkaVariant::I16,
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DataType::I24 => LdPkaVariant::I24,
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DataType::I32 => LdPkaVariant::I32,
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DataType::I48 => LdPkaVariant::I48,
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DataType::I64 => LdPkaVariant::I64,
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DataType::I96 => LdPkaVariant::I96,
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DataType::I128 => LdPkaVariant::I128,
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_ => return None,
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};
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LdPka::get_info(variant, arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(LdPka {
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variant: match self.dst_type {
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DataType::I8 => LdPkaVariant::I8,
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DataType::I16 => LdPkaVariant::I16,
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DataType::I24 => LdPkaVariant::I24,
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DataType::I32 => LdPkaVariant::I32,
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DataType::I48 => LdPkaVariant::I48,
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DataType::I64 => LdPkaVariant::I64,
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DataType::I96 => LdPkaVariant::I96,
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DataType::I128 => LdPkaVariant::I128,
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t => panic!("LD_PKA.{t} not supported"),
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},
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access: self.access.into(),
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extend: SignExtendOrNoneM::None,
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message_slot_index: e.get_msg_slot_idx().unwrap(),
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sr_dst: op_encode_sr_write(self, &self.dst),
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src0: op_encode_src(self, &self.offset),
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src1: op_encode_src(self, &self.handle),
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})
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}
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}
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impl V9Instr for OpLeaPka {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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LeaPka::get_info((), arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(LeaPka {
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message_slot_index: e.get_msg_slot_idx().unwrap(),
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sr_dst: op_encode_sr_write(self, &self.dst),
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src0: op_encode_src(self, &self.offset),
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src1: op_encode_src(self, &self.handle),
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})
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}
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}
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impl V9Instr for OpLoad {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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let variant = match self.dst_type {
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DataType::I8 => LoadVariant::I8,
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DataType::I16 => LoadVariant::I16,
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DataType::I24 => LoadVariant::I24,
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DataType::I32 => LoadVariant::I32,
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DataType::I48 => LoadVariant::I48,
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DataType::I64 => LoadVariant::I64,
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DataType::I96 => LoadVariant::I96,
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DataType::I128 => LoadVariant::I128,
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_ => return None,
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};
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Load::get_info(variant, arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(Load {
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variant: match self.dst_type {
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DataType::I8 => LoadVariant::I8,
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DataType::I16 => LoadVariant::I16,
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DataType::I24 => LoadVariant::I24,
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DataType::I32 => LoadVariant::I32,
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DataType::I48 => LoadVariant::I48,
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DataType::I64 => LoadVariant::I64,
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DataType::I96 => LoadVariant::I96,
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DataType::I128 => LoadVariant::I128,
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t => panic!("LOAD.{t} not supported"),
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},
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access: self.access.into(),
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extend: SignExtendOrNoneM::None,
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message_slot_index: e.get_msg_slot_idx().unwrap(),
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sr_dst: op_encode_sr_write(self, &self.dst),
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src0: op_encode_src(self, &self.addr),
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offset: self.offset,
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})
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}
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}
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impl V9Instr for OpMov {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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if let SrcRef::Imm32(_) = &self.src.src_ref {
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let variant = match self.dst_type {
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DataType::I16 => MovImmVariant::V2i16,
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DataType::I32 => MovImmVariant::I32,
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_ => return None,
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};
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MovImm::get_info(variant, arch)
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} else {
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let variant = match self.dst_type {
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DataType::I32 => MovVariant::I32,
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_ => return None,
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};
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Mov::get_info(variant, arch)
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}
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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if let SrcRef::Imm32(imm) = &self.src.src_ref {
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e.encode(MovImm {
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variant: match self.dst_type {
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DataType::I16 => MovImmVariant::V2i16,
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DataType::I32 => MovImmVariant::I32,
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t => panic!("MOV_IMM.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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imm1w: *imm,
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})
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} else {
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e.encode(Mov {
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variant: match self.dst_type {
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DataType::I32 => MovVariant::I32,
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t => panic!("MOV.{t} not supported"),
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},
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dst: op_encode_dst(self, &self.dst),
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src0: op_encode_src(self, &self.src),
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})
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}
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}
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}
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impl V9Instr for OpNop {
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fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
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Nop::get_info((), arch)
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}
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fn encode(&self, e: V9Encoder) -> EncodedInstr {
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e.encode(Nop {})
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}
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}
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macro_rules! shift_lop_info {
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($op:expr, $Instr:ident, $arch:expr) => {
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paste! {{
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let variant = match $op.dst_type {
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DataType::I32 => [<$Instr Variant>]::I32,
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DataType::I64 => [<$Instr Variant>]::I64,
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DataType::V2I16 => [<$Instr Variant>]::V2i16,
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DataType::V4I8 => [<$Instr Variant>]::V4i8,
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_ => return None,
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};
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$Instr::get_info(variant, $arch)
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}}
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};
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}
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macro_rules! shift_lop_as {
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($op:expr, $Instr:ident) => {
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paste! {
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|
|
@ -320,268 +735,72 @@ macro_rules! shift_lop_as {
|
|||
};
|
||||
}
|
||||
|
||||
struct InstrEnc {
|
||||
arch: u8,
|
||||
fau_page_index: u8,
|
||||
flow: FlowControlM,
|
||||
}
|
||||
impl V9Instr for OpShiftLop {
|
||||
fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
|
||||
use LogicOp::*;
|
||||
use ShiftOp::*;
|
||||
match (self.shift_op, self.logic_op) {
|
||||
(LShift, And) => shift_lop_info!(self, LshiftAnd, arch),
|
||||
(LShift, Or) => shift_lop_info!(self, LshiftOr, arch),
|
||||
(LShift, Xor) => shift_lop_info!(self, LshiftXor, arch),
|
||||
(RShift, And) => shift_lop_info!(self, RshiftAnd, arch),
|
||||
(RShift, Or) => shift_lop_info!(self, RshiftOr, arch),
|
||||
(RShift, Xor) => shift_lop_info!(self, RshiftXor, arch),
|
||||
(ARShift, _) => shift_lop_info!(self, Arshift, arch),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
impl InstrEnc {
|
||||
fn encode(
|
||||
self,
|
||||
instr: impl TryEncode<Encoded = [u32; 2], Error: std::fmt::Debug>,
|
||||
) -> [u32; 2] {
|
||||
let mut bits = instr
|
||||
.try_encode(self.arch)
|
||||
.expect("Failed to encode instruction");
|
||||
let flow = self
|
||||
.flow
|
||||
.try_encode(self.arch)
|
||||
.expect("Failed to encode flow");
|
||||
|
||||
let mut b = BitMutView::new(&mut bits);
|
||||
b.set_field(57..59, self.fau_page_index);
|
||||
b.set_field(59..63, flow);
|
||||
|
||||
bits
|
||||
fn encode(&self, e: V9Encoder) -> EncodedInstr {
|
||||
use LogicOp::*;
|
||||
use ShiftOp::*;
|
||||
match (self.shift_op, self.logic_op) {
|
||||
(LShift, And) => e.encode(shift_lop_as!(self, LshiftAnd)),
|
||||
(LShift, Or) => e.encode(shift_lop_as!(self, LshiftOr)),
|
||||
(LShift, Xor) => e.encode(shift_lop_as!(self, LshiftXor)),
|
||||
(RShift, And) => e.encode(shift_lop_as!(self, RshiftAnd)),
|
||||
(RShift, Or) => e.encode(shift_lop_as!(self, RshiftOr)),
|
||||
(RShift, Xor) => e.encode(shift_lop_as!(self, RshiftXor)),
|
||||
(ARShift, _) => {
|
||||
assert!(self.shift.is_zero());
|
||||
e.encode(Arshift {
|
||||
variant: match self.dst_type {
|
||||
DataType::I32 => ArshiftVariant::I32,
|
||||
DataType::I64 => ArshiftVariant::I64,
|
||||
DataType::V2I16 => ArshiftVariant::V2i16,
|
||||
DataType::V4I8 => ArshiftVariant::V4i8,
|
||||
t => panic!("SHIFT_LOP.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(self, &self.dst),
|
||||
not_result: self.not_result.into(),
|
||||
src0: op_encode_src(self, &self.src0),
|
||||
src1: op_encode_src(self, &self.shift),
|
||||
})
|
||||
}
|
||||
_ => todo!("Implement [lr]rot"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn encode_instr(
|
||||
ip: i64,
|
||||
instr: &Instr,
|
||||
arch: u8,
|
||||
labels: &FxHashMap<Label, i64>,
|
||||
) -> [u32; 2] {
|
||||
let msg_slot_idx = instr.flow.get_msg_slot_idx().map(|idx| match idx {
|
||||
0 => MessageSlotIndexM::Slot0,
|
||||
1 => MessageSlotIndexM::Slot1,
|
||||
2 => MessageSlotIndexM::Slot2,
|
||||
_ => panic!("Invalid message slot"),
|
||||
});
|
||||
impl V9Instr for OpStore {
|
||||
fn get_info(&self, arch: u8) -> Option<&'static InstructionInfo> {
|
||||
let variant = match self.src_type {
|
||||
DataType::I8 => StoreVariant::I8,
|
||||
DataType::I16 => StoreVariant::I16,
|
||||
DataType::I24 => StoreVariant::I24,
|
||||
DataType::I32 => StoreVariant::I32,
|
||||
DataType::I48 => StoreVariant::I48,
|
||||
DataType::I64 => StoreVariant::I64,
|
||||
DataType::I96 => StoreVariant::I96,
|
||||
DataType::I128 => StoreVariant::I128,
|
||||
_ => return None,
|
||||
};
|
||||
Store::get_info(variant, arch)
|
||||
}
|
||||
|
||||
let enc = InstrEnc {
|
||||
arch,
|
||||
fau_page_index: instr_fau_page(instr).unwrap_or(0),
|
||||
flow: encode_flow(instr.flow, arch),
|
||||
};
|
||||
|
||||
match &instr.op {
|
||||
Op::Branch(op) => enc.encode(Branch {
|
||||
not: op.not.into(),
|
||||
src0: op_encode_src(op, &op.cond),
|
||||
combine: match op.combine_op {
|
||||
BranchCombineOp::None => BranchCombineM::And,
|
||||
BranchCombineOp::H0 => BranchCombineM::H0,
|
||||
BranchCombineOp::H1 => BranchCombineM::H1,
|
||||
BranchCombineOp::And => BranchCombineM::Lowbits,
|
||||
BranchCombineOp::LowBits => BranchCombineM::None,
|
||||
},
|
||||
conservative: false.into(),
|
||||
offset: labels.get(&op.label).unwrap() - (ip + INSTR_SIZE),
|
||||
}),
|
||||
Op::FAdd(op) => {
|
||||
if let SrcRef::Imm32(imm) = &op.srcs[1].src_ref {
|
||||
enc.encode(FaddImm {
|
||||
variant: match op.dst_type {
|
||||
DataType::F32 => FaddImmVariant::F32,
|
||||
DataType::V2F16 => FaddImmVariant::V2f16,
|
||||
t => panic!("FADD_IMM.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
imm1w: *imm,
|
||||
})
|
||||
} else {
|
||||
enc.encode(Fadd {
|
||||
variant: match op.dst_type {
|
||||
DataType::F32 => FaddVariant::F32,
|
||||
DataType::V2F16 => FaddVariant::V2f16,
|
||||
t => panic!("FADD.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
src1: op_encode_src(op, &op.srcs[1]),
|
||||
clamp: ClampM::None,
|
||||
round: Round::None,
|
||||
sticky: false.into(),
|
||||
})
|
||||
}
|
||||
}
|
||||
Op::FCmp(op) => enc.encode(Fcmp {
|
||||
variant: match op.src_type {
|
||||
DataType::F32 => FcmpVariant::F32,
|
||||
DataType::V2F16 => FcmpVariant::V2f16,
|
||||
t => panic!("FCMP.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
src1: op_encode_src(op, &op.srcs[1]),
|
||||
cmpf: match op.cmp_op {
|
||||
CmpOp::Eq => CmpfM::Eq,
|
||||
CmpOp::Gt => CmpfM::Gt,
|
||||
CmpOp::Ge => CmpfM::Ge,
|
||||
CmpOp::Ne => CmpfM::Ne,
|
||||
CmpOp::Lt => CmpfM::Lt,
|
||||
CmpOp::Le => CmpfM::Le,
|
||||
CmpOp::GtLt => CmpfM::Gtlt,
|
||||
CmpOp::Total => CmpfM::Total,
|
||||
},
|
||||
result_type: CmpResultTypeM::M1,
|
||||
}),
|
||||
Op::IAdd(op) => {
|
||||
if let SrcRef::Imm32(imm) = &op.srcs[1].src_ref {
|
||||
enc.encode(IaddImm {
|
||||
variant: match op.dst_type {
|
||||
DataType::I32 => IaddImmVariant::I32,
|
||||
DataType::V2I16 => IaddImmVariant::V2i16,
|
||||
DataType::V4I8 => IaddImmVariant::V4i8,
|
||||
t => panic!("IADD_IMM.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
imm1w: *imm,
|
||||
})
|
||||
} else {
|
||||
enc.encode(Iadd {
|
||||
variant: match op.dst_type {
|
||||
DataType::S32 => IaddVariant::S32,
|
||||
DataType::S64 => IaddVariant::S64,
|
||||
DataType::U32 => IaddVariant::U32,
|
||||
DataType::U64 => IaddVariant::U64,
|
||||
DataType::V2S16 => IaddVariant::V2s16,
|
||||
DataType::V2U16 => IaddVariant::V2u16,
|
||||
DataType::V4S8 => IaddVariant::V4s8,
|
||||
DataType::V4U8 => IaddVariant::V4u8,
|
||||
t => panic!("IADD.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
src1: op_encode_src(op, &op.srcs[1]),
|
||||
saturate: op.saturate.into(),
|
||||
})
|
||||
}
|
||||
}
|
||||
Op::ICmp(op) => enc.encode(Icmp {
|
||||
variant: match op.src_type {
|
||||
DataType::S32 => IcmpVariant::S32,
|
||||
DataType::U32 => IcmpVariant::U32,
|
||||
DataType::V2S16 => IcmpVariant::V2s16,
|
||||
DataType::V2U16 => IcmpVariant::V2u16,
|
||||
t => panic!("FCMP.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.srcs[0]),
|
||||
src1: op_encode_src(op, &op.srcs[1]),
|
||||
cmpf: match op.cmp_op {
|
||||
CmpOp::Eq => CmpfM::Eq,
|
||||
CmpOp::Gt => CmpfM::Gt,
|
||||
CmpOp::Ge => CmpfM::Ge,
|
||||
CmpOp::Ne => CmpfM::Ne,
|
||||
CmpOp::Lt => CmpfM::Lt,
|
||||
CmpOp::Le => CmpfM::Le,
|
||||
cmp_op => panic!("Unsupported comparison: {cmp_op}"),
|
||||
},
|
||||
result_type: CmpResultTypeM::M1,
|
||||
}),
|
||||
Op::LdPka(op) => enc.encode(LdPka {
|
||||
variant: match op.dst_type {
|
||||
DataType::I8 => LdPkaVariant::I8,
|
||||
DataType::I16 => LdPkaVariant::I16,
|
||||
DataType::I24 => LdPkaVariant::I24,
|
||||
DataType::I32 => LdPkaVariant::I32,
|
||||
DataType::I48 => LdPkaVariant::I48,
|
||||
DataType::I64 => LdPkaVariant::I64,
|
||||
DataType::I96 => LdPkaVariant::I96,
|
||||
DataType::I128 => LdPkaVariant::I128,
|
||||
t => panic!("LD_PKA.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
extend: SignExtendOrNoneM::None,
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.offset),
|
||||
src1: op_encode_src(op, &op.handle),
|
||||
}),
|
||||
Op::LeaPka(op) => enc.encode(LeaPka {
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.offset),
|
||||
src1: op_encode_src(op, &op.handle),
|
||||
}),
|
||||
Op::Load(op) => enc.encode(Load {
|
||||
variant: match op.dst_type {
|
||||
DataType::I8 => LoadVariant::I8,
|
||||
DataType::I16 => LoadVariant::I16,
|
||||
DataType::I24 => LoadVariant::I24,
|
||||
DataType::I32 => LoadVariant::I32,
|
||||
DataType::I48 => LoadVariant::I48,
|
||||
DataType::I64 => LoadVariant::I64,
|
||||
DataType::I96 => LoadVariant::I96,
|
||||
DataType::I128 => LoadVariant::I128,
|
||||
t => panic!("LOAD.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
extend: SignExtendOrNoneM::None,
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_dst: op_encode_sr_write(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.addr),
|
||||
offset: op.offset,
|
||||
}),
|
||||
Op::Mov(op) => {
|
||||
if let SrcRef::Imm32(imm) = &op.src.src_ref {
|
||||
enc.encode(MovImm {
|
||||
variant: match op.dst_type {
|
||||
DataType::I16 => MovImmVariant::V2i16,
|
||||
DataType::I32 => MovImmVariant::I32,
|
||||
t => panic!("MOV_IMM.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
imm1w: *imm,
|
||||
})
|
||||
} else {
|
||||
enc.encode(Mov {
|
||||
variant: match op.dst_type {
|
||||
DataType::I32 => MovVariant::I32,
|
||||
t => panic!("MOV.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
src0: op_encode_src(op, &op.src),
|
||||
})
|
||||
}
|
||||
}
|
||||
Op::Nop(_) => enc.encode(Nop {}),
|
||||
Op::ShiftLop(op) => {
|
||||
use LogicOp::*;
|
||||
use ShiftOp::*;
|
||||
match (op.shift_op, op.logic_op) {
|
||||
(LShift, And) => enc.encode(shift_lop_as!(op, LshiftAnd)),
|
||||
(LShift, Or) => enc.encode(shift_lop_as!(op, LshiftOr)),
|
||||
(LShift, Xor) => enc.encode(shift_lop_as!(op, LshiftXor)),
|
||||
(RShift, And) => enc.encode(shift_lop_as!(op, RshiftAnd)),
|
||||
(RShift, Or) => enc.encode(shift_lop_as!(op, RshiftOr)),
|
||||
(RShift, Xor) => enc.encode(shift_lop_as!(op, RshiftXor)),
|
||||
(ARShift, _) => {
|
||||
assert!(op.shift.is_zero());
|
||||
enc.encode(Arshift {
|
||||
variant: match op.dst_type {
|
||||
DataType::I32 => ArshiftVariant::I32,
|
||||
DataType::I64 => ArshiftVariant::I64,
|
||||
DataType::V2I16 => ArshiftVariant::V2i16,
|
||||
DataType::V4I8 => ArshiftVariant::V4i8,
|
||||
t => panic!("SHIFT_LOP.{t} not supported"),
|
||||
},
|
||||
dst: op_encode_dst(op, &op.dst),
|
||||
not_result: op.not_result.into(),
|
||||
src0: op_encode_src(op, &op.src0),
|
||||
src1: op_encode_src(op, &op.shift),
|
||||
})
|
||||
}
|
||||
_ => todo!("Implement [lr]rot"),
|
||||
}
|
||||
}
|
||||
Op::Store(op) => enc.encode(Store {
|
||||
variant: match op.src_type {
|
||||
fn encode(&self, e: V9Encoder) -> EncodedInstr {
|
||||
e.encode(Store {
|
||||
variant: match self.src_type {
|
||||
DataType::I8 => StoreVariant::I8,
|
||||
DataType::I16 => StoreVariant::I16,
|
||||
DataType::I24 => StoreVariant::I24,
|
||||
|
|
@ -592,17 +811,49 @@ fn encode_instr(
|
|||
DataType::I128 => StoreVariant::I128,
|
||||
t => panic!("LOAD.{t} not supported"),
|
||||
},
|
||||
access: op.access.into(),
|
||||
message_slot_index: msg_slot_idx.unwrap(),
|
||||
sr_src: op_encode_sr_read(op, &op.data),
|
||||
src0: op_encode_src(op, &op.addr),
|
||||
offset: op.offset,
|
||||
}),
|
||||
op => panic!("Instruction not encoded: {op}"),
|
||||
access: self.access.into(),
|
||||
message_slot_index: e.get_msg_slot_idx().unwrap(),
|
||||
sr_src: op_encode_sr_read(self, &self.data),
|
||||
src0: op_encode_src(self, &self.addr),
|
||||
offset: self.offset,
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
const INSTR_SIZE: i64 = size_of::<<Mov as TryEncode>::Encoded>() as i64;
|
||||
macro_rules! v9_op_match {
|
||||
($op: expr, |$x: ident| $y: expr) => {
|
||||
match $op {
|
||||
Op::Branch($x) => $y,
|
||||
Op::FAdd($x) => $y,
|
||||
Op::FCmp($x) => $y,
|
||||
Op::IAdd($x) => $y,
|
||||
Op::ICmp($x) => $y,
|
||||
Op::LdPka($x) => $y,
|
||||
Op::LeaPka($x) => $y,
|
||||
Op::Load($x) => $y,
|
||||
Op::Mov($x) => $y,
|
||||
Op::Nop($x) => $y,
|
||||
Op::ShiftLop($x) => $y,
|
||||
Op::Store($x) => $y,
|
||||
_ => panic!("Unsupported op: {}", $op),
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
fn encode_instr(
|
||||
ip: i64,
|
||||
instr: &Instr,
|
||||
arch: u8,
|
||||
labels: &FxHashMap<Label, i64>,
|
||||
) -> [u32; 2] {
|
||||
let e = V9Encoder {
|
||||
ip,
|
||||
instr,
|
||||
arch,
|
||||
labels,
|
||||
};
|
||||
v9_op_match!(&instr.op, |op| op.encode(e))
|
||||
}
|
||||
|
||||
pub fn encode_v9(s: &Shader<'_>, arch: u8) -> Vec<u32> {
|
||||
let mut labels = FxHashMap::default();
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue