Commit graph

90581 commits

Author SHA1 Message Date
Kevin Zhao
8912862a40 amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Frans Gu
acaeae2861 amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
2017-03-30 14:44:33 +02:00
Xavi Zhang
90029b958e amdgpu/addrlib: Stylish cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Roy Zhan
554c1b9f2d amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled
Experiment show 1D tiling + TcCompatible cannot work together.
2017-03-30 14:44:33 +02:00
Xavi Zhang
120a5d0e42 amdgpu/addrlib: fix pixel index calculation of thick micro tiling 2017-03-30 14:44:33 +02:00
Xavi Zhang
199912a9bc amdgpu/addrlib: Add a flag to skip calculate indices
This is useful for debugging and special cases for stencil surfaces
do not require texture fetch compatible.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
10f7d1cb03 amdgpu/addrlib: add equation generation
1. Add new surface flags needEquation for client driver use to force
the surface tile setting equation compatible. Override 2D/3D macro
tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1.
2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure
to return number of equations and the equation table to client driver
3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to
return the equation index to client driver

Please note the use of address equation has following restrictions:
1) The surface can't be splitable
2) The surface can't have non zero tile swizzle value
3) Surface with > 1 slices must have PRT tile mode, which disable
slice rotation
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
3e44337bd6 amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness 2017-03-30 14:44:33 +02:00
Xavi Zhang
79dcda5116 amdgpu/addrlib: add define HAVE_TSERVER 2017-03-30 14:44:33 +02:00
Frans Gu
7293a020bd amdgpu/addrlib: Add new interface to support macro mode index query 2017-03-30 14:44:33 +02:00
Roy Zhan
c16e1e2041 amdgpu/addrlib: add explicit Log2NonPow2 function 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
4a4b7da141 amdgpu/addrlib: Fix invalid access to m_tileTable
Sometimes client driver passes valid tile info into address library,
in this case, the tile index is computed in function
HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg.
We need to call HwlPostCheckTileIndex to calculate the correct tile
index to get tile split bytes for this case.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
9e40e09089 amdgpu/addrlib: add ADDR_ANALYSIS_ASSUME
It helps fix analysis warnings in MSC.
2017-03-30 14:44:33 +02:00
XiaoYuan Zheng
6164f23a91 amdgpu/addrlib: add tcCompatible htile addr from coordinate support. 2017-03-30 14:44:33 +02:00
Carlos Xiong
3bd1380ab2 amdgpu/addrlib: force all zero tile info for linear general. 2017-03-30 14:44:33 +02:00
Nicolai Hähnle
8b110f0319 amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW
When clients queries tile Info from tile index and expects accurate
tileSplit info,  bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.
2017-03-30 14:44:33 +02:00
Frans Gu
ca6a38fd6a amdgpu/addrlib: Refine the PRT tile mode selection
Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.
2017-03-30 14:44:33 +02:00
Xavi Zhang
2bf243f7c6 amdgpu/addrlib: add dccRamSizeAligned output flag
This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
e443b48966 amdgpu/addrlib: Change comment alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
e06aeaf19f amdgpu/addrlib: style changes and minor cleanups
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
cb5d22a3f3 amdgpu/addrlib: AddrLib inheritance refactor
Add one more abstraction layer into inheritance system.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
52a1288a15 amdgpu/addrlib: rearrange code in preparation of refactoring
No code changes.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Xavi Zhang
f12d430c59 amdgpu/addrlib: add disableLinearOpt flag 2017-03-30 14:44:33 +02:00
Xavi Zhang
b5d8120a07 amdgpu/addrlib: Add GetMaxAlignments 2017-03-30 14:44:33 +02:00
Xavi Zhang
3c3d620cf3 amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding path
Kaveri (2-pipe) macro tiling mode table was initially set to all
4-aspect-ratio so the swizzling path did not work for it and then we
chose to pad the offset. We now discover the root cause is that if
ratio > 2, the swizzling path does not work. So we can safely use the
same path for Kaveri.
2017-03-30 14:44:33 +02:00
Xavi Zhang
3614999878 amdgpu/addrlib: Rewrite tile mode optmization code
Note: remove reference to degrade4Space and use opt4Space instead.
2017-03-30 14:44:33 +02:00
Carlos Xiong
c12e35065a amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.
Even if surface info input flag "tcComaptible" is enabled, tc
compatible may be not supported if tile split happens for depth
surfaces. Add a new flag in output structure to notify client to
disable tc compatible in this case.
2017-03-30 14:44:33 +02:00
Xavi Zhang
2ffb30c2af amdgpu/addrlib: Make comments shorter
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
XiaoYuan Zheng
3c7bd4e013 amdgpu/addrlib: add new flag nonSplit
Flag tcCompatible has different usage in CI and VI. Add a new flag
"nonSplit" for CI.
2017-03-30 14:44:33 +02:00
Xiao-Tao Zai
47de94a794 amdgpu/addrlib: allow tileSplitBytes greater than row size
Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp
depth surface. Remove the sanity check that tileSplitBytes must be
greater than row size. There could be performance loss but may be
covered by non-split depth which enables tc-compatible read.
2017-03-30 14:44:33 +02:00
Carlos Xiong
d52e0bbfe6 amdgpu/addrlib: Change to compute TC compatible stencil info
Change the logic to compute tc compatible stencil info via depth's
tileIndex instead of using depth's tileInfo. So the clients can get
the stencil's tileInfo computed from macroModeTable. If the stencil
tileInfo is same as depth tileInfo, then stencil is tc compatible;
otherwise, stencil is not tc compatible. The current suggestion is to
create another stencil buffer with the tc compatible tileInfo, use
depth-to-color copy to decompress and tile convert the rendered
stencil to tc compoatible stencil (And use the new stencil buffer to
program TC).
2017-03-30 14:44:33 +02:00
Nicolai Hähnle
6c65f256e2 amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spelling
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Marek Olšák
6e44087e77 configure.ac: require libdrm_amdgpu 2.4.76 for Vega
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:42:06 +02:00
Samuel Pitoiset
e7850bb7f0 st/glsl_to_tgsi: use glsl_type::sampler_index()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 13:15:34 +02:00
Samuel Pitoiset
784d3a7066 glsl: allow glsl_type::sampler_index() with images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 13:15:16 +02:00
Nicolai Hähnle
257ee3f7ef st/mesa: improve error messages and fix security warning
Debian, Ubuntu set default build flag: -Werror=format-security

  CC       state_tracker/st_cb_texturebarrier.lo
state_tracker/st_cb_eglimage.c: In function ‘st_egl_image_get_surface’:
state_tracker/st_cb_eglimage.c:64:7: error: format not a string literal and no format arguments [-Werror=format-security]
       _mesa_error(ctx, GL_INVALID_VALUE, error);
       ^~~~~~~~~~~
state_tracker/st_cb_eglimage.c:71:7: error: format not a string literal and no format arguments [-Werror=format-security]
       _mesa_error(ctx, GL_INVALID_OPERATION, error);
       ^~~~~~~~~~~

Reported-by: Krzysztof Kolasa <kkolasa@winsoft.pl>
Fixes: 83e9de25f3 ("st/mesa: EGLImageTarget* error handling")
2017-03-30 11:24:36 +02:00
Kenneth Graunke
e4dc005bce i965: Combine intel_batchbuffer_reloc and intel_batchbuffer_reloc64
These two functions do the exact same thing.  One returns a uint64_t,
and the other takes the same uint64_t and truncates it to a uint32_t.

We only need the uint64_t variant - the caller can truncate if it wants.
This patch gives us one function, intel_batchbuffer_reloc, that does
the 64-bit thing.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-03-30 00:15:28 -07:00
Kenneth Graunke
5177231670 i965: Use WARN_ONCE instead of open coding it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-03-30 00:15:09 -07:00
Harish Krupo
36cb2003f1 android: pass sse4.1 flag as appropriate
We have functions which depend on sse4.1 support but we didnt pass
the right compile flag for it. This patch fixes it.

Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-03-30 08:02:49 +03:00
Dave Airlie
a930c2c612 radv: fix mask attribs properly.
some days it just doesn't pay to get out of bed.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-30 13:09:30 +10:00
Dave Airlie
aa27a9f687 radv: fix regression with mask attrib setting code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-30 12:07:32 +10:00
Dave Airlie
2b35b60df1 radv: move to using nir clip/cull merge pass.
Doing this before tessellation makes doing some bits of
tessellation a bit cleaner. It also cleans up a bit of the
llvm generator code.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-03-30 11:04:56 +10:00
George Kyriazis
5079c277b5 swr: [scons] Fix windows build
Fix codegen build break that was introduced earlier

v2: update rules for gen_knobs.cpp and gen_knobs.h

v3: Introduce bldroot and revert generator file changes, making patch simpler.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2017-03-29 18:52:07 -05:00
Craig Stout
1da7a11de8 anv/cmd_buffer: fix host memory leak
push_constants must be free'd.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100452
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
2017-03-29 14:32:32 -07:00
Timothy Arceri
16debc652a mesa/glthread: fallback to sync if count validation fails
The old code would sync and then throw a cryptic error message.
There is no need for a custom error, we can just fallback to
the real function and have it do proper validation.

Fixes piglit test:
glsl-uniform-out-of-bounds

Which was returning the wrong error code.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 08:23:00 +11:00
Timothy Arceri
18f4c93b02 mesa/glthread: add async support to glProgramUniform*() functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 08:22:51 +11:00
Timothy Arceri
1ea73b9c61 mesa/glthread: print out syncs when MARSHAL_MAX_CMD_SIZE is exceeded
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 08:19:07 +11:00
Jason Ekstrand
9aba81b160 anv/batch_chain: Handle another OOM in cmd_buffer_execbuf
Found by inspection while rebasing other patches.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-03-29 09:39:49 -07:00
Philipp Zabel
83e9de25f3 st/mesa: EGLImageTarget* error handling
Stop trying to specify texture or renderbuffer objects for unsupported
EGL images. Generate the error codes specified in the OES_EGL_image
extension.

EGLImageTargetTexture2D and EGLImageTargetRenderbuffer would call
the pipe driver's create_surface callback without ever checking that
the given EGL image is actually compatible with the chosen target
texture or renderbuffer. This patch adds a call to the pipe driver's
is_format_supported callback and generates an INVALID_OPERATION error
for unsupported EGL images. If the EGL image handle does not describe
a valid EGL image, an INVALID_VALUE error is generated.

v2: fixed get_surface to actually use the usage and error parameters

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-29 18:04:42 +02:00
Philipp Zabel
d10172d527 st/mesa: move st_manager_get_egl_image_surface into st_cb_eglimage.c
The only callers are here, and we will add generation of GL errors in
the following patch.  Rename the function to st_egl_image_get_surface,
pass the gl_context instead of st_context, and move the cast from
GLeglImageOES to void* into st_egl_image_get_surface.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-29 18:04:12 +02:00